Hi everyone, I am looking for information about how to design a capacitor DAC layout for a 10-bit SAR ADC to get better matching. If anyone knows a good reference, I would really appreciate your help.

What I have done in the past is to make a unit capacitor that is the size of the "LSB" capacitor. Then when I layout the capacitor area, the "LSB" capacitor (also known as the bit_0 capacitor) will be 1 unit capacitor. The "LSB+1" capacitor (also known as the bit_1 capacitor) will be 2 unit capacitors. Continuing all the way up to the "MSB" capacitor (also known as the bit_9 capacitor) will be 512 unit capacitors.

@Larry Harris Thank you Larry for the information. I am looking for a reference to compare different CDAC layout approaches like this one.

yes, the layout looks reasonable.

Yes. Thank you. I know this capacitor should always connect to the supply rail.

👍

Look into Alan Hastings' book on Art of Analog Layout. In his chapter on capacitors he mentions some references regarding CDAC layouts

@Reza Papi: Also take a look at the one I designed, which is at https://github.com/RTimothyEdwards/sky130_ef_ip__cdac3v_12bit, which is a split-array DAC with offset trim. In addition to the split array, my approach differs by using more radially-symmetric arrangement of caps, and I adopted a switching method that incorporates the sample & hold into the capacitor array and keeps the output centered around a common-mode voltage, so the comparator does not need to operate rail-to-rail.

Thank you Koustubh.

@Reza Papi: I used stacked MiM caps because they're available in sky130 and reduce the amount of space by half compared to a single MiM cap.

Thank you @Tim Edwards.

Hi @Reza Papi one last thing to consider is the mismatch between the capacitors on the outside of the cap array layout with the capacitors on the inside of the cap array layout. From a Photolithographic effect, the outside capacitors are adjacent to open space, whereas the inside capacitors are adjacent to other capacitors. The outside edge of the array will have a slightly different size due to the difference in the Photolithographic environment. What I do is to add a row of "spare capacitors" all away around the capacitor array. I would then short out the "spare capacitors" to ground. This will increase the layout area of your final capacitor array, however, this will remove the Photolithographic effect mismatch of your capacitors.

@Larry Harris, @Reza Papi: One reason I chose the split-array architecture was that I was able to put dummy capacitors around the entire perimeter of the array without feeling like the whole DAC was taking up an inordinate amount of area.

Thank you @Larry Harris @Tim Edwards for the tips. I really appreciate that. Yes, for the last tapeout I used this layout floor plan for the DAC. The DAC is surrounded by dummy capacitors. I was looking for more efficient and better floorpaln.