Hi everyone, I'm currently working with OpenLane for synthesizing my FFT design, and I’m encountering an issue where some memories seem to be replaced by registers during the synthesis process, but I'm unsure if any modules are being blackboxed. Here’s a summary of the situation: • I’ve successfully synthesis my rtl code in yosys. • There are warnings in the Yosys log about certain memories (

\result_i_ns

,

\result_r_ns

,

\result_i

,

\result_r

) being replaced by registers. • When running the

blackbox

command, no specific blackboxed modules are reported. Any advice or pointers on how to handle this situation would be greatly appreciated! Thanks in advance! 🙏

@Goutham Krishnan P Can you share your

designs/fft/config.json

file along with the linter error log?

@Mitch Bailey these are the files

Hmmm. Can you share the

synthesis/blackbox/sky130_fd_sc_hd__blackbox.v

file?

sky130_fd_sc_hd__blackbox.v

@Goutham Krishnan P thanks for sharing. I’m not an expert, but the only reason I can think of you might have an older version of verilator. What files do you have in src/?

You don’t have

sky130_fd_sc_hd__blackbox.v

there, right? I’m guessing that the system automatically adds that.

yes it is

@Goutham Krishnan P If

sky130_fd_sc_hd__blackbox.v

is in the

src

directory, can you try removing it? I don’t think I’ve seen any designs that explicitly use that file. Another way might be to explicitly list the files in

VERILOG_FILES

.