Hi Everyone, I’ve implemented an FFT algorithm in Python and would now like to translate it into RTL (e.g., Verilog).Could someone guide me? Thanks in advance!!

I personally found it helpful to translate the design into something closer to hardware like C and the C was easier to translate into hardware youll likely have some butterfly unit and a RAM to store samples and some FSM that iterates computing 2-point butterfly pairs I found it helpful to look at the xilinx docs for their FFT core just to get a sense of landscape of design possibilities

thank you @Julian Kemmerer