I am having problems understanding the varactor sch symbol, how should it be wired? Consider the test I am making, should this work? I was expecting several pF for a 5x5 varactor from the sky130 docs (https://antmicro-skywater-pdk-docs.readthedocs.io/en/latest/rules/device-details.html) , but this is oscilating at frequencies much higher than expected.

This is the way i simulated the capacitance and compared with a same size nmos transistor. A 5x5 varactor has max 0.2pF caacitance when biased above 0.7V.

Hey Stefan, thank you for your answer. The magic cell for the varactor is different from a nfet, it is a ndiff inside a nwell inside a pwell, maybe more like a pfet. I think the n+ (ndiff I assume) areas act like contacts to the nwell, I dont understand what the 'b' terminal is in this case. If the 'b' is connected to the guard ring in the pwell area, I understand it must be gnd, but if this is related to the nwell area, it would be vdd. (See my pin connection understanding in the images) I need to use this in a differential setup for a VCO in which I dont think i can control one pin voltage that must be dc tied to vdd (see my sch in the images). In this setup, my vtune isnt vtuning =(

yes the varactor is more similar to a pfet. However capacitance can never deviate much from a 5x5 LV oxide capacitance which is ~0.2pF. I believe these devices are used in accumulation, so source/drain/pwell tap are connected to GND.

This is nice, the shift to the right is equal to the voltage applied to the c1 terminal, so its effect seems to be exactly opposite to the gate (c0) terminal.