Hello, I'm attempting to perform a post layout simulation of an inverter to complete part of the open source workflow. According to magic and netgen, it is DRC and LVS clean. The resulting graph displays not the expected INV waveform. I have included a PPT that documented what I did. I like to ask is there a setting in magic and xchem that I need to set or turn on to make sure the simulation is correct? Thank you!

From what I see, the subcircuit is declared with port order "A OUT VP VN" in the netlist, but in the testbench you have instantiated the inverter with port order "VDD A OUT GND".

Thank you for the input. So to make this work does that mean I have to define the INV schematic's and symbol's port order (the shift-s command?) or only the schematic? Also is it best to just regenerate the symbol after specifying the schematic port order? A follow up question is, once I set port order on the INV schematic, do I have to repeat the same move as in the test bench as well?

Well, in principle you should make sure that the layout's port order agrees with the schematic, so that it is easier to swap one for the other in the testbench (also give the cells the same name, so that the only thing you need to change in the testbench to switch between schematic and layout is the include file). However, in my reading of your document, it looks like your schematic and layout subcircuits do agree on port order. It's just the testbench that's wrong. To make sure the layout's port order matches the schematic's, select each port label in the layout and type the command

port index <value>

.

I understand. For now by rearranging the port number in the layout .spice file to reflect the port order generated by the test bench made it work. Going forward I will take care to configure the port orders from schematic and layout plus all the way to the testbench. By the way, what would you recommend to perform parasitic simulations? Is the method going to be the same as the post layout sim?

You may have difficulty keeping magic from renumbering the port indexes if you're trying to renumber them to indexes that are already being used; the best thing to do is to note that the order is what's important, not the actual index. So do

port last

to find out what the highest number index is, and then, starting with port A, number them sequentially starting 1 higher than whatever was returned by

port last

. Or, a possibly simpler solution is to hand-edit the .mag file for the subcircuit, find the labels at the bottom, each of which will have a "port" line after it with the port index, and just change all the indexes to what you want them to be (I do that myself more than I care to admit).