I was looking at the STA results for MPW2, and I wonder if we are missing constraints for the gpio serial clock. I added this to `caravel.sdc`:

## GPIO clock
create_generated_clock -name gpio_clock -divide_by 2 -source \
   [get_pins housekeeping/wb_clk_i] [get_pins housekeeping/serial_clock]

## Ignore the reset line
set_false_path -through [get_pins housekeeping/serial_resetn]

# There is a false timing path from the housekeeping macro through to GPIO 3
# back to the housekeeping macro then back out to the GPIOs. (I presume it's
# the housekeeping SPI slave).
set_false_path -through [get_nets {mprj_io[3]}]

set_propagated_clock [get_clocks gpio_clock]

I'm not 100% sure of the above, but I do see hold violations where I didn't before. The larger ones are specific to the bit bang interface, which we might be able to mitigate by setting one signal at a time (set data in one transaction, then toggle clock in another). With the paths through the bit bang interface ignored, I see a couple of small hold violations (0.5ns). Considering how conservative the STA is (the SDC adds timing derating, clock uncertainty etc), maybe it's ok, but I thought I'd mention it.