Hi , is there any limitation on number of ports of the design ? I am getting below error . Plus what is the deffault size of the floorplan that is assumed ? I am getting a warning " Current core area is too small for a power grid."
[STEP 1]
[INFO]: Running Synthesis...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis...
[STEP 3]
[INFO]: Running Initial Floorplanning...
[WARNING]: Current core area is too small for a power grid. The power grid will be minimized.
[INFO]: Setting Core Dimensions...
[STEP 4]
[INFO]: Running IO Placement...
[ERROR]: during executing openroad script /openlane/scripts/openroad/ioplacer.tcl
[ERROR]: Exit code: 1
[ERROR]: full log: designs/reram_instruction_decoder/runs/RUN_2022.08.29_12.23.52/logs/floorplan/4-io.log
[ERROR]: Last 10 lines:
[INFO ODB-0128] Design: instruction_decoder_RRAM
[INFO ODB-0130] Created 150 pins.
[INFO ODB-0131] Created 140 components and 881 component-terminals.
[INFO ODB-0133] Created 172 nets and 208 connections.
[INFO ODB-0134] Finished DEF file: /openlane/designs/reram_instruction_decoder/runs/RUN_2022.08.29_12.23.52/tmp/floorplan/3-initial_fp.def
Found 0 macro blocks.
Using 1u default distance from corners.
[ERROR PPL-0024] Number of pins 150 exceeds max possible 132.
Error: ioplacer.tcl, 60 PPL-0024
child process exited abnormally