open-source-silicon.dev

Hi,

I got an error _*[ERROR DRT-0302] Unsupported multiple pins on bterm vccd1*_ during Detailed Routing phase. Searched in slack or openlane github issues but couldn't manage to find anything.

The design has 6 macros and the fail is during the flow of user_project_wrapper where only macros are instantiated and connected.

The repo is: <https://github.com/mbaykenar/mpw7_yonga_soc>

```set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(SYNTH_DEFINES) "USE_POWER_PINS"```

YOu define a top level pin vccd1 because you unconditionally define USE_POWER_PINS.

You cant have a net and a pin connected to it that is both signal and power.

<@U030SLWD34M>
Solution: Comment out `set ::env(SYNTH_DEFINES) "USE_POWER_PINS"`

Thanks a lot, but when I comment out this, I got error below:

ERROR: Module `sky130_sram_2kbyte_1rw1r_32x512_8' referenced in module `user_project_wrapper' in cell `data_ram' does not have a port named 'vssd1'

1. <https://github.com/mbaykenar/mpw7_yonga_soc/blob/f148ffe706fbe96bad7efc471aebabd3748d6011/verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v#L5|https://github.com/mbaykenar/mpw7_yonga_soc/blob/f148ffe706fbe96bad7efc471aebabd37[…]/verilog/rtl/rtl/components/sky130_sram_2kbyte_1rw1r_32x512_8.v>

Again, unconditionally declared define of USE_POWER_PINS.

<https://armleo-openlane.readthedocs.io/en/merge-window-4/docs/source/openram.html#power-ground-nets>

Use `SYNTH_USE_PG_PINS_DEFINES` to allow automatic parsing of the power/ground nets.
```"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",```
This will run synthesis without USE_POWER_PINS to generate the final verilog and then another synthesis with USE_POWER_PINS defined to generate the powered verilog netlist.

If you unconditionally define the USE_POWER_PINS then powered netlist is generated properly, but the synthesis netlist is generated with signal port vccd1, which should not exist because it is not powered netlist

thanks a lot. now I have same errors for other macros that I have hardened with unconditionally defines inside verilog codes

then I need to re-harden my macros without unconditionally define USE_POWER_PINS and in config.tcl file only set SYNTH_USE_PG_DEFINES to "USE_POWER_PINS"

vccd1 should be marked as a power pin but it seems it isn't in your case which is why you get this error

i will reharden my macros and retry it thanks