Hi all, I have a query regarding openlane flow process ... i am trying to do the layout for a frequency divider design using openlane ... i am going through the advanced physical layout design course in which picorv32a design is taken and layout steps are carried out .. i am able to do the same .. But when it comes to implementing the same on my design i am not able to get to a value on fp_core_util and clk period. For fp_core_util above 40 in run_placement i am getting an error as shown in the pictures during global placement step, and when i try fp_core_util below 40 i am getting a warning as attached in image but when i do this i am getting a negative slack (around -0.1) as well and drc errors are popping up (i tried the above combinations with clk periods of 5, 10, 12 and 24). When i am giving fp_sizing as absolute and give a die area as 500x500 i get the layout without any errors, warnings and drcs. i am attaching the error (for util above 40), warning(for util below 40) and the json file i am modifying. can anyone please help me figure this out. Thanks in advance !

The 3rd screenshot shows flow complete successful. You may take that configuration and further optimize PPA @Dantu Nandini Devi

You should be able to get it to work with a fixed die size.

Higher the

CORE_UTIL

lesser die area. Lower the the

CORE_UTIL

increased die size. That is why with

CORE_UTIL 40

working,

CORE_UTIL 70

getting placement congestion

the 3rd snapshot says core area is too small with 40% util. Lower core util has increased die size, not sure why the snapshot error says the other way round ?

Yes sir fixed die area is working properly with 500×500 dimensions and 70 util