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Hi, <https://github.com/efabless/sky130_sram_macros>, for srams in this github, what is the access latency when reading the sram?

There is information in the .html file. Note, however, this is an analytical prediction still, so it is not very accurate.

You should make sure to use the dev branch for the most recent memories.

by the way, does these srams have 2 access latency ? just want to have a double confim.

take below sram for an example :
module sky130_sram_1kbyte_1rw1r_32x256_8(`ifdef USE_POWER_PINS    vccd1,    vssd1,`endif// Port 0: RW    clk0,csb0,web0,wmask0,addr0,din0,dout0,// Port 1: R    clk1,csb1,addr1,dout1  );

if cycle 0 csb0 is low, web0 is high,  cycle 2 read data will be valid on dout0 ?

sorry, I got some mismatch, cycle 1 read data will be valid on dout0, but in the second half clock cycle.

That is correct. Data is valid after the negative clock edge

You should assume the memory takes the full clock cycle