open-source-silicon.dev

Hi, Does anyone know If Can I use the 4 SRAM that there are in sky130_sram_macros?

You can. The newest are in the dev branch. Only the 1k has been verified in hardware. The timing models are still questionable.

I've tried simulations and builds for the 1k 8x1024 one.
<https://github.com/Cra2yPierr0t/Vthernet-SoC/blob/main/verilog/rtl/user_project_wrapper.v#L133|https://github.com/Cra2yPierr0t/Vthernet-SoC/blob/main/verilog/rtl/user_project_wrapper.v#L133>

<@U03CSQTGFM2> the 32 bit one not the 8 bit

<@U02BMCBFRK3> there seems to be a bug in that. You can't arbitrarily change the wmask without recompiling the macro... This might leave some bits disconnected.

<@U02BMCBFRK3> the dev one has an updated Verilog as well

There actually isn't a wmask at all for that one, just web0 since it is byte write

20220818_030425.jpg

<@U0175T39732> Thanks for the reply!
I know there is a bug regarding the 1k 8x1024 wmask. This is because if the bit width of the wmask is [0:0], it will probably cause an LVS Error as shown in the image, so the bit width of the wmask is changed as a countermeasure.
Has this been updated?
I couldn't find the repository to create an issue.

<@U02BMCBFRK3> It is fixed in the dev branch. You should use that macro

Nobody submitted a bug but we fixed it in OpenRAM

<@U0175T39732> 
Amazing! You fixed it!
I wish I had the knowledge and skills to commit to OpenRAM.

<@U02BMCBFRK3> If you find bugs, please file them. If you reference one of the sky130-sram-macros, we can use it as a test case and fix it

<@U0175T39732> Roger that! I will try to do so.