open-source-silicon.dev

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Hello <@U017UPJEGKZ>,
We are using the nmos_waffle from open_pmic. You isolated it, right?
In the layout of the power_stage, did you connect the 2nd guard ring of the nmos to GND? Shouldn't it be connected to Drain or Vdd?

In normal cases you connect the deep nwell to the positive supply rail, where it allows you to run the containing pwell at a voltage that is different from the substrate voltage.

In my case though the NMOS is already ground reference. I connected the deep nwell to ground to short out the parasitic NPN BJT

the deep nwell is really not doing anything in my design except making it a bit more robust to latch-up / possibly increasing efficiency slightly.

You have a NPN transistor between the nmos drain/source diffusions, the pwell, and whatever N well is near by. When you have a reverse current on the nmos you are injecting current though the base. If the nearby N well structures are VDD tied you will pull current from VDD. If you use deep nwell isolation connected to VSS you are shorting out that path