Hey everyone. Dumb question. if I am instantiating something as an IP in openlane, why do I stil have to give verilog files? doesnot make sense

The synthesis still needs to know about the block. That can either be done with a liberty file or a verilog file. The latter doesn't need to contain anything it can be an empty module with the

(* blackbox *)

attribute but it needs to define the corrects ports.

so in the top level i instantiate this IP . write blackbox above it and then put lef,def and gds , will it be fine?

You can put it in the same file that's fine.

okay thankyou. hopefully it will help. I dont have the verilog files for this Ip and just have the lef, def and gds files so was a little confused what to do

Beware that without a liberty file, timing won't be analyzed which depending on what the IP is, might not be good.

oh yes i do have that too