Hi everyone, is there any reason that DRC in klayout using the sky130A_mr.drc runset would result in

OFFGRID vertex on <http://areaid.re|areaid.re>

when creating a route with licon? Is it because there are 90 degree bends in the route, by using Box tool and Path tool? I will resort to using unconnected licon boxes instead as this is just used to connect li with tap - not necessary to have a continuous licon for this. Separately, I am seeing the same issue with capm.2b and capm.2b_a for mim_cap cells - would be any particular reason to see this same

OFFGRID

error if the cap is placed properly on a 0.005 grid? The edge pairs in the image of the capm issues show that they lie on a 0.005 grid. Thanks - let me know if any more information would be helpful! (cc @Elpida Karapepera @Ahmed Aboulsaad)

@Matthew Siyu Chen In the first case, the rule being violated is not

OFFGRID vertex on <http://areaid.re|areaid.re>

, but rather

licon.1

. It’s not a 0.17um square. In the second case, the rules being violated are

capm.2b

and

capm.2b_a

. You should be able to find the corresponding rule definitions in this document. Have you tried the

Tools

->

Marker Browser

in klayout?

Hi @Matthew Siyu Chen As Mitch pointed out, load the xml file into klayout and view the DRC errors overlaying the layout in klayout. Also, you cannot route in licon. As Mitch said licon must be a 0.17um square except in a precision resistor when it can be slotted. It cannot be routed. Regarding the capm.2b and capm.2b_a errors: Please post the error markers overlayed on the layout in a screen shot. We have an issue in the capm.2b check and it incorrectly flags some geometries. I don't think the capm.2b_a rules have the same issue, though. Those are likely real errors. Again, though, post screenshots of the error markers and I will verify.

@David Lindley @Mitch Bailey Thank you! I think I have a good understanding of the issues. I will use the

guard_ring_gen

in the PCells library instead to avoid manually placing 0.17um squares. And this is an image of the capm.2b issues - my bottom_plate is definitely too close to metal3. This didn't come up as an issue in the previous klayout runset I was using. Separately,

cap_m

spacing of 1.27um is only applicable to separate mimcap devices, right? I have two connected in parallel on the right with 0.95um spacing between capm layers, and two separate mimcap devices on the left with 1.65um spacing (greater than the 1.27um requirement) - is the 0.95um spacing for parallel mimcaps valid (I see no issues in the DRC output)? Thank you

The bottom plate rule is applicable if the met3 is not continuous.