vks
07/13/2023, 7:51 AMopen mpw
and chipignite
shuttles ? Are there any limitations while using Klayout with these pdks? What I found is that pcells for all devices in sky130 is not available for klayout.Filippo
07/18/2023, 7:44 AMJuan Andres
07/23/2023, 8:44 PMJuan Andres
07/23/2023, 10:30 PMJuan Andres
07/24/2023, 2:23 AMJuan Andres
07/24/2023, 2:57 AMJuan Andres
07/24/2023, 4:31 AMPatricio Carrasco
07/24/2023, 4:36 PMPatricio Carrasco
07/24/2023, 10:58 PMKennedy Caisley
07/25/2023, 6:04 PMvks
07/28/2023, 7:43 AMvks
07/28/2023, 11:14 AMKLAYOUT_HOME=$PDK_ROOT/$PDK/libs.tech/klayout klayout -e
to invoke klayout with sky130 pdk. But only layer nos. are visible on layers pallete and not names. Need to manually import .lyp
file everytime in order to see layer names inside klayout. Can you suggest solution to this issue.yrrapt
07/28/2023, 7:03 PMJuan Andres
08/03/2023, 8:51 PMKrzysztof Herman
08/11/2023, 6:18 AM<https://github.com/KrzysztofHerman/OpenROAD-flow-scripts/blob/ihp-platform/flow/platforms/sky130hd/fill.json>
one but for other technology (IHP130)vks
08/22/2023, 9:47 AMyrrapt
08/22/2023, 9:58 AMJC
09/03/2023, 10:39 PMJørgen Kragh Jakobsen
09/08/2023, 7:14 PMMuhammad Zeeshan
09/26/2023, 4:43 PMaquiles viza
10/02/2023, 8:46 PM> python E:\Descargas\ic_analog\code\layout\globalfoundries-pdk-libs-gf180mcu_fd_pv\klayout\drc\run_drc.py --variant=C --path=RING_PAD.gds --verbose
02-Oct-2023 17:10:41 | INFO | Your Klayout version is: KLayout 0.28.12
02-Oct-2023 17:10:41 | INFO | Your Klayout version is: KLayout 0.28.12
02-Oct-2023 17:10:41 | INFO | ## Generating template with for the following rule tables: ['comp.drc', 'contact.drc', 'dnwell.drc', 'drc_bjt.drc', 'dualgate.drc', 'dummy_exclude.drc', 'efuse.drc', 'esd.drc', 'hres.drc', 'ldnmos.drc', 'ldpmos.drc', 'lres.drc', 'lvpwell.drc', 'lvs_bjt.drc', 'mcell.drc', 'metal1.drc', 'metal2.drc', 'metal3.drc', 'metal4.drc', 'metal5.drc', 'metaltop.drc', 'metaltop_30k.drc', 'mim_a.drc', 'mim_b.drc', 'nat.drc', 'nplus.drc', 'nwell.drc', 'otp_mk.drc', 'poly2.drc', 'pplus.drc', 'pres.drc', 'sab.drc', 'sram_3p3.drc', 'sram_5p0.drc', 'via1.drc', 'via2.drc', 'via3.drc', 'via4.drc', 'via5.drc', 'ymtp_mk.drc']
02-Oct-2023 17:10:41 | INFO | ## Your run dir located at: E:\Descargas\ic_analog\code\layout\drc_run_2023_10_02_20_10_41
02-Oct-2023 17:10:41 | INFO | Running Global Foundries 180nm MCU E:\Descargas\ic_analog\code\layout\RING_PAD.gds checks on design main on cell RING_PAD:
Traceback (most recent call last):
File "E:\Descargas\ic_analog\code\layout\globalfoundries-pdk-libs-gf180mcu_fd_pv\klayout\drc\run_drc.py", line 693, in <module>
main(drc_run_dir, arguments)
File "E:\Descargas\ic_analog\code\layout\globalfoundries-pdk-libs-gf180mcu_fd_pv\klayout\drc\run_drc.py", line 650, in main
run_single_processor(
File "E:\Descargas\ic_analog\code\layout\globalfoundries-pdk-libs-gf180mcu_fd_pv\klayout\drc\run_drc.py", line 601, in run_single_processor
run_check(drc_file, "main", layout_path, drc_run_dir, switches)
File "E:\Descargas\ic_analog\code\layout\globalfoundries-pdk-libs-gf180mcu_fd_pv\klayout\drc\run_drc.py", line 452, in run_check
check_call(run_str, shell=True)
File "E:\source\mambaforge\envs\chipathon\Lib\subprocess.py", line 413, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command 'klayout -b -r E:\Descargas\ic_analog\code\layout\drc_run_2023_10_02_20_10_41\main.drc -rd thr=2 -rd run_mode=flat -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd verbose=true -rd feol=true -rd beol=true -rd offgrid=true -rd conn_drc=false -rd density=false -rd slow_via=false -rd topcell=RING_PAD -rd input=E:\Descargas\ic_analog\code\layout\RING_PAD.gds -rd report=E:\Descargas\ic_analog\code\layout\drc_run_2023_10_02_20_10_41\RING_PAD_main.lyrdb -rd table_name=main' returned non-zero exit status 1.
Executing the last message without -b flag gives this error:
> klayout -r E:\Descargas\ic_analog\code\layout\drc_run_2023_10_02_20_10_41\main.drc -rd thr=2 -rd run_mode=flat -rd metal_top=9K -rd mim_option=B -rd metal_level=5LM -rd verbose=true -rd feol=true -rd beol=true -rd offgrid=true -rd conn_drc=false -rd density=false -rd slow_via=false -rd topcell=RING_PAD -rd input=E:\Descargas\ic_analog\code\layout\RING_PAD.gds -rd report=E:\Descargas\ic_analog\code\layout\drc_run_2023_10_02_20_10_41\RING_PAD_main.lyrdb -rd table_name=main
NoMethodError: undefined method `strip' for nil:NilClass in Executable::execute
E:\Descargas\ic_analog\code\layout\drc_run_2023_10_02_20_10_41\main.drc:29:in `block in execute'
C:/Users/akiles/AppData/Roaming/Klayout/lib/ruby/3.0.0/logger.rb:586:in `format_message'
C:/Users/akiles/AppData/Roaming/Klayout/lib/ruby/3.0.0/logger.rb:476:in `add'
C:/Users/akiles/AppData/Roaming/Klayout/lib/ruby/3.0.0/logger.rb:529:in `info'
E:\Descargas\ic_analog\code\layout\drc_run_2023_10_02_20_10_41\main.drc:36:in `execute'
:/built-in-macros\drc_interpreters.lym:31:in `instance_eval'
:/built-in-macros\drc_interpreters.lym:31:in `execute'
Running the Precheck DRC with klayout in GUI mode, gives this log error:
> klayout -r E:\Descargas\ic_analog\code\layout\mpw_precheck\checks\tech-files\gf180mcuC_mr.drc
NoMethodError: undefined method `strip' for nil:NilClass in Executable::execute
E:\Descargas\ic_analog\code\layout\mpw_precheck\checks\tech-files\gf180mcuC_mr.drc:39:in `getMemSize'
E:\Descargas\ic_analog\code\layout\mpw_precheck\checks\tech-files\gf180mcuC_mr.drc:118:in `block in execute'
C:/Users/akiles/AppData/Roaming/Klayout/lib/ruby/3.0.0/logger.rb:586:in `format_message'
C:/Users/akiles/AppData/Roaming/Klayout/lib/ruby/3.0.0/logger.rb:476:in `add'
C:/Users/akiles/AppData/Roaming/Klayout/lib/ruby/3.0.0/logger.rb:529:in `info'
E:\Descargas\ic_analog\code\layout\mpw_precheck\checks\tech-files\gf180mcuC_mr.drc:129:in `execute'
:/built-in-macros\drc_interpreters.lym:31:in `instance_eval'
:/built-in-macros\drc_interpreters.lym:31:in `execute'
I'm posting the drc generated by the run_drc.py
script, but I think that is more a missing dependency inside Klayout's ruby packed version.Ruibin Mao
10/04/2023, 1:52 AMRuibin Mao
10/06/2023, 6:23 AMSebastian Sanchez
10/12/2023, 8:49 PMrun_lvs.py
script for a simple inverter from this repo: https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pv/tree/mainand and I got that the netlist don't match. To check if I was doing something wrong I tried with a nfet pcell but also got that the netlist don't match. I think that the labels are being misinterpreted while running the lvs since the nodes in the .cir file are named by numbers instead of the actual labels.Charly Meyer
10/23/2023, 10:31 AMvks
11/02/2023, 2:14 PMpsdm
layer are coming. I tried to rectify them by putting extra psdm
layer wherever errors are coming inside klayout in edit mode. But this selected layer is not getting drawn as shown in attached video. Please suggets how to make it work.vks
11/04/2023, 6:04 AMaquiles viza
11/06/2023, 9:44 PMLEEJA J
11/19/2023, 3:36 PMAtif Khan
11/24/2023, 6:52 AM