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Hi where can I get the list of devices we should not use in sky130 pdk ? <@U06H50VMDPU> did mention me some devices in pdk don’t work?

Hi <@U053UFMPKDW>, `no_synth.cells` is found in the sky130 PDK in the path `./libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells` and a copy of that can be seen *<https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/openlane/sky130_fd_sc_hd/no_synth.cells|here>*.

thats weird. i ran a simple code on openlane and it did use cell in the list. pls see buffer in image.  <@U016EM8L91B> 

<@U016EM8L91B> <@U020J2W6Q84> am I wrong about the intent of `./libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells` and <https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/openlane/sky130_fd_sc_hd/no_synth.cells> ? Certainly I found one user who used a cell from this list and it DID have weird routing problems where it tried to connect a wire/via in an incorrect place... but on the other hand several of these cells DO show up in PnR layouts produced by OpenLane 1.

`no_synth` only excludes the cell in question from synthesis. PnR is still allowed to use these cells. There is a separate file for cells excluded because of DRC issues, which is: <https://github.com/RTimothyEdwards/open_pdks/blob/master/sky130/openlane/sky130_fd_sc_hd/drc_exclude.cells>

The reason for this is, for example, Yosys would use clock buffers instead of normal buffers for non-clock signals. Clock buffers have symmetrical rise/fall and take a little bit more area, which doesn't make sense for non-clock signals.

So that's why clock buffers are excluded from no_synth. However, they must be used for the clock tree during PnR.

Is using ms library safe ? sky130/openlane/sky130_fd_sc_ms . I am having issues with hd library in proprietary software 

It is not as heavily tested as `_hd` and there's an inherent risk because of that.

Fantastic, thanks <@U020J2W6Q84>! That's good clarification and I overlooked `drc_exclude.cells`. Great to know (and also good that it's a much smaller list :wink: )