Hi, I'm getting "Top level cell failed pin matching" while integrating my design as a black box in caravel user_project_wrapper. What could I be doing wrong?

Hard to tell without more information (lvs reports). What pins are failing?

I see

Final result: 
Circuits match uniquely.

Can you share this

/home/ubuntu/caravel_user_project/openlane/s3chip/runs/24_11_04_16_06/logs/signoff/41-s3chip.lef.lvs.log

? It has more detailed results.

sorry that was the incorrect log file. I meant to share this one: https://0x0.st/XGU3.lvs.log

Unused power in the layout

Cell user_project_wrapper (0) disconnected node: vccd1
Cell user_project_wrapper (0) disconnected node: vccd2
Cell user_project_wrapper (0) disconnected node: vdda1
Cell user_project_wrapper (0) disconnected node: vdda2
Cell user_project_wrapper (0) disconnected node: vssa1
Cell user_project_wrapper (0) disconnected node: vssa2
Cell user_project_wrapper (0) disconnected node: vssd1
Cell user_project_wrapper (0) disconnected node: vssd2

unused power in verilog

Cell user_project_wrapper (1) disconnected node: vccd2
Cell user_project_wrapper (1) disconnected node: vdda1
Cell user_project_wrapper (1) disconnected node: vdda2
Cell user_project_wrapper (1) disconnected node: vssa1
Cell user_project_wrapper (1) disconnected node: vssa2
Cell user_project_wrapper (1) disconnected node: vssd2

vccd1

and

vssd1

are not connected to anything in the layout. That’s what’s causing the port mismatch.

My configs are the default ones and I get this when I try to integrate my design as a black box into the wrapper. While running the flow, I got a warning along the lines of "die area is small, so power grid will be scaled down". Could that cause this error? My RTL uses the default

`ifdef USE_POWER_PINS
    .vccd1(vccd1),      // User area 1 1.8V power
    .vssd1(vssd1),      // User area 1 digital ground
`endif

macros in the definitions, so not sure what I'm doing wrong here.

If the macro height is less than about 250um (I think), then, depending on the placement, it may not intersect with the correct power grid. You can force your macro to be larger by using

"FP_SIZING": "absolute",
"DIE_SIZE": "0 0 250 250",

or you can reposition it so that it intersects with the correct power rails.

I tried with a larger area but that makes it fail at the irdrop report step

Open the gds, and look at the power rail locations and the macro position and adjust accordingly.

thanks a lot! I shifted the placement in my `macro.cfg`and got a passing LVS just now.