Jazoolee Ahamed
10/30/2024, 3:10 AMMitch Bailey
10/30/2024, 4:20 AMJazoolee Ahamed
10/30/2024, 7:27 AMJazoolee Ahamed
10/30/2024, 8:50 AMJazoolee Ahamed
10/30/2024, 8:51 AMMitch Bailey
10/30/2024, 9:28 AMDavid Lindley
10/30/2024, 12:05 PMJazoolee Ahamed
10/30/2024, 2:23 PMMitch Bailey
10/30/2024, 2:36 PMlvs_config.json
file. The $LVS_ROOT/tech/$PDK/lvs_config.sram.json
file contains the necessary spice files.
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"SRAM_MACRO": "sky130_sram_2kbyte_1rw1r_32x512_8",
"INCLUDE_CONFIGS": [
"$LVS_ROOT/tech/$PDK/lvs_config.base.json",
"$LVS_ROOT/tech/$PDK/lvs_config.sram.json"
],
Jazoolee Ahamed
10/31/2024, 10:55 AMJazoolee Ahamed
10/31/2024, 10:56 AM{
"TOP_SOURCE": "user_project_wrapper",
"TOP_LAYOUT": "$TOP_SOURCE",
"EXTRACT_FLATGLOB": [
""
],
"EXTRACT_ABSTRACT": [
"*__fill_*",
"*__fakediode_*",
"*__tapvpwrvgnd_*"
],
"LVS_FLATTEN": [
""
],
"LVS_NOFLATTEN": [
""
],
"LVS_IGNORE": [
""
],
"LVS_SPICE_FILES": [
"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
],
"LVS_VERILOG_FILES": [
"$UPRJ_ROOT/verilog/gl/SLRV.v",
"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
],
"LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds",
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"SRAM_MACRO": "sky130_sram_2kbyte_1rw1r_32x512_8",
"INCLUDE_CONFIGS": [
"$LVS_ROOT/tech/$PDK/lvs_config.base.json",
"$LVS_ROOT/tech/$PDK/lvs_config.sram.json"
],
}
Mitch Bailey
10/31/2024, 12:14 PM{
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"SRAM_MACRO": "sky130_sram_2kbyte_1rw1r_32x512_8",
"INCLUDE_CONFIGS": [
"$LVS_ROOT/tech/$PDK/lvs_config.base.json",
"$LVS_ROOT/tech/$PDK/lvs_config.sram.json"
],
"TOP_SOURCE": "user_project_wrapper",
"TOP_LAYOUT": "$TOP_SOURCE",
"EXTRACT_FLATGLOB": [
""
],
"EXTRACT_ABSTRACT": [
"*__fill_*",
"*__fakediode_*",
"*__tapvpwrvgnd_*"
],
"LVS_FLATTEN": [
""
],
"LVS_NOFLATTEN": [
""
],
"LVS_IGNORE": [
""
],
"LVS_SPICE_FILES": [
"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
],
"LVS_VERILOG_FILES": [
"$UPRJ_ROOT/verilog/gl/SLRV.v",
"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
],
"LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
}
LVS_ROOT
is the directory in mpw_precheck that contains the programs and configuration files. Usually, $PRECHECK_ROOT/checks/be_checks
. It is set in the precheck program so you should not set it.Jazoolee Ahamed
10/31/2024, 1:19 PMMitch Bailey
10/31/2024, 2:07 PM{
"STD_CELL_LIBRARY": "sky130_fd_sc_hd",
"SRAM_MACRO": "sky130_sram_2kbyte_1rw1r_32x512_8",
"INCLUDE_CONFIGS": [
"$LVS_ROOT/tech/$PDK/lvs_config.base.json",
"$LVS_ROOT/tech/$PDK/lvs_config.sram.json"
],
"TOP_SOURCE": "user_project_wrapper",
"TOP_LAYOUT": "$TOP_SOURCE",
"EXTRACT_FLATGLOB": [
""
],
"EXTRACT_ABSTRACT": [
""
],
"LVS_FLATTEN": [
""
],
"LVS_NOFLATTEN": [
""
],
"LVS_IGNORE": [
""
],
"LVS_SPICE_FILES": [
""
],
"LVS_VERILOG_FILES": [
"$UPRJ_ROOT/verilog/gl/SLRV.v",
"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
],
"LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
}
The deleted lines are already in the included files.