Can someone help me with this hold violations? When I include my design file inside the user_proj_example I don't get any hold violations anywhere, but when I harden my design separately without putting it inside the user_proj_example, it still doesn't give me any errors, but the moment i harden it with make user_proj_wrapper I'm getting this hold violations. Why would this make a difference? Also I tried editing the wrapper config files with PL/GLB_RESIZER_HOLD_SLACK_MARGIN, PL/GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT, IO_PCT but nothing solves this issue

@Jazoolee Ahamed When you instantiate a hard macro into

user_project_wrapper

, there will be added wiring to connect the

user_project_wrapper

pins to the hard macro. This added wiring will effect the timing results. You can either eliminate the hard macro and flatten the design in

user_project_wrapper

or add timing constraints to the

user_proj_example

sdc file (I think). I don’t have the instructions on how to do either of those at hand, but you can search for them.

Increase hold margin during macro hardening itself, and try to integrate it

This is an issue and valid one. If hard macro is instantiated inside project wrapper the timing violation pops up. In general, adding flops at the inputs of the hard macro may solve the issue. Registering inputs inside hard macro sometimes help to avoid timing violations.

@Vijayan Krishnan Hold slack margin of the macro is already at 0.8, should I increase it even more?

Otherwise change synthesis strategy and try. In wrapper level no standard cell included right?

@Vijayan Krishnan yeah, no standard cell in the wrapper level, what do you mean by synthesis strategy? In the config?

SYNTH_STRATEGY