Hello, I am getting an out of bounds error when trying to synthesize my design, but as far as I know, nothing is getting referenced that is out of bounds. Does anybody know a workaround?

Can you share your openlane log?

Yes, of course. Here it is: https://justpaste.it/cq4zi

copy and paste error log from terminal. In synthesis log we don't see any error

Right, here is that: https://justpaste.it/9uadl

There’s this

/home/nikolababic/FP_Adder/openlane/user_proj_example/../../verilog/rtl/addRecFN.v:138: Warning: Range [2:1] select out of bounds on signal `\alignDist': Setting 1 MSB bits to undef.

Yes, but running the testbench, I do not get any errors or warning. And that is a module from the HardFloat library, which should work fine. I've checked the code and there shouldn't be any out of bounds errors.

Simulation may make assumptions that synthesis doesn’t. Can you share

verilog/rtl/addRecFN.v

?

Yes: https://repositories.efabless.com/nikolab2809/UNIC_CASS_FP_Adder/blob/main/f/verilog/rtl/addRecFN.v

alignDist[(alignDistWidth - 1):2], far_roundExtraMask); alignDistWidth value is 2. so range becomes [1:2]

Yes, but in the design used sigWidth is 24, so alignDistWidth becomes 4, I believe.

ohh ok. need to check netlist for resolved values.

@Nikola Babić are you still having trouble with this? You could try putting a

$display(...)

statement below line 68 to see what value is being resolved for sigWidth, alignDistWidth, and any others. The output from $display will go into the synthesis log (so make it a string you can search for easily like "`@@@ LOOK HERE FOR sigWidth: ...`") and it should also get displayed when you run your simulation.

@Anton Maurovic (efabless support) Sorry for the late response. I have found the issue. Seems that local parameters can't be synthesized or something, so I have just swapped them with constants.