module design13 #(parameter WIDTH = 4) (input logic [(WIDTH-1):0] a,

input logic [(WIDTH-1):0] b,

input logic [(WIDTH-1):0] c,

output logic [(WIDTH+1):0] out);

logic [WIDTH:0] ps,cs,pr,gn;

logic [WIDTH+1:0] fc,fs,ipr,ign,temp;

always_comb begin

cs[0] = 1'b0;

ps[WIDTH]=1'b0;

ps= {1'b0, a ^ (b ^ c)};

cs = {(a & b) | (c & (a | b)),1'b0};

pr = ps | cs;

gn = ps^cs;

ipr = {1'b0,pr};

ign = {1'b0,gn};

fs  = {1'b0,ps};

fc[0] = 0;

for(int i=1; i<WIDTH+1; i++) begin

fc[i] = ign[i-1] | (ipr[i-1] & fc[i-1]);

end

out = fc ^ fs;

end

endmodule

I get this warning:

%Warning-ALWCOMBORDER: /home/npn/my_designs/design13/design13.sv:21:17: Always_comb variable driven after use: 'fc'

: ... note: In instance 'design13'

21 |                 fc[i] = ign[i-1] | (ipr[i-1] & fc[i-1]);

──────────────────────────────────────────────────── Yosys Synth Checks ─────────────────────────────────────────────────────

[15:08:12] VERBOSE  Running 'Checker.YosysSynthChecks'…                                                          step.py:1088

[15:08:12] ERROR    1 Yosys check errors found.                                                                checker.py:128

Classic - Stage 8 - Yosys Synth Checks ━━━╸━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━  7/76 0:00:17

[15:08:12] WARNING  The following warnings were generated by the flow:                                            flow.py:672

[15:08:12] WARNING  [Checker.LintWarnings] 1 Lint warnings found.                                                 flow.py:674

[15:08:12] ERROR    The following error was encountered while running the flow:                               __main__.py:160

1 Yosys check errors found.

[15:08:12] ERROR    OpenLane will now quit.

And this error shows... It seems there is something wrong with the for loop... What is it?

Can you please send the logs

image.png

I would disable the warning

What comment?

... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message.

In the systemverilog code?

Yeah

At the beginning?

It needs to be around the source with the warning

IMG_20241021_223123.jpg

You need to send the error logs

Ok where do I find them?

For that particular stage the errors are embedded in the yosys logs

Ok will check that

You go to the folder for yosys synthesis under your run

Then?