Hey everyone! I've been testing the #C0161A4A59V-flow-scripts with the built-in GCD design using the Nangate45 library, and I noticed something interesting between different #Yosys versions. When synthesizing with (the old) Yosys 0.37+64, the design ends up with 365 cells and a chip area estimate of 523.754, but with (the new) Yosys 0.43, it jumps to 503 cells and an area estimate of 650.104! Both runs use the same design file and constraints. (detailed comparison below). So I'm curious if anyone else has noticed similar behavior or has insights on how can I make orfs/yosys/abc optimize for area? What are the available switches and knobs in ORFS to make it optimize for area as much as possible? It seems like there's no way to increase the effort put in by yosys/abc, it takes ~1 seconds and it calls it a day. I've tried

export RESYNTH_AREA_RECOVER = 1

- it has no effect. Do you recommend that I use the older version if area is what I'm after? Any tips or suggestions would be much appreciated! 😊 Nangate45 GCD Design Comparison: * Yosys 0.37+64 (git sha1 bbb8ad599) AND Yosys 0.36: - ORFS commit: Earlier this year (0adaebe958681ae37a4c431081eba33f27a87411) Cells: 365 Chip Area: 523.754 Core Area: 899.346 Instance Count: 471 Instance Area: 615.79 Critical Path Delay: 0.4598 Critical Path Slack: -0.0918 Total Power: 2.30e-03 * Yosys 0.43 (git sha1 ead4718e5): - ORFS commit: latest (091a06bfa82f55e01fcdb456efe9580a3b2d8a63) Cells: 503 Chip Area: 650.104 Core Area: 1149.12 Instance Count: 663 Instance Area: 841.89 Critical Path Delay: 0.4223 Critical Path Slack: -0.0543 Total Power: 3.15e-03 P.S.: The newer Yosys version (0.43) is generating more complex logic by introducing more gates, especially in INV (inverters), NAND, AOI21, and AND gates while the usage of multiplexer and XOR/XNOR gates has decreased, indicating that the synthesis tool might be replacing complex gates with combinations of simpler gates to achieve a shorter critical path.

You could try setting

ABC_AREA=1

in your config file, that's about the only knob there is. Otherwise you would want to look into a custom ABC script.

Thank you Austin, yes I'm using

ABC_AREA=1

. I've looked into writing a custom one but since tool versions matter a lot I was not so sure. Could you point me to examples/docs of abc scripts that target the area?

You'll want to look and ask at the yosys GitHub. I don't have much experience with abc scripts.

For reference: https://github.com/YosysHQ/yosys/discussions/4600

I mean if you care about area above all else, you could even do a ripple-carry adder instead of Brent-Kung

Ripple-carry adder has the least gate-count but post-layout Brent-Kung wins. I haven't tried the ripple-carry, not sure how to. But there's a neat comparison different adders in the reference I linked.

If you haven't turned down the clock period yet, then that's something you'll have to do first. RCA is significantly slower and you won't realize the area gains unless you reduce the clock constraints. Otherwise OR will try to buffer and resize to make up for it.

So OR will try and implement RCA if the clock period allows it? Is there a switch or a file for the RCA I need to add first?

No, you would need to specify it to yosys (not sure how to do that). But OR will insert a lot of buffers and increase the area in order to meet timing if it isn't meeting timing.