Check out Dinesh Annaya's @Dinesh A RISCduino design that uses a hierarachical design methodology and other interesting design concepts to achieve good PPA and timing closure using OpenROAD and OpenLane. https://theopenroadproject.org/implementation-of-riscduino-core-using-a-hierarchical-design-flow/

@Vijayan Krishnan @Matt Liberty ORFS generates a synth_stat.txt after synthesis. It gives this

Chip area for module

what are the units for this value? Attaching the file for same.

Hi, may I ask how do we interpret the MTerms in SPEF file? Take for example the image shown, we have the normal mapping of

cells

to alphabet pins, but mapping of

nets

(e.g. *37) to numbers. How can we check which number correspond to which part of the

net

?

Hello everyone, could anyone confirm me if openROAD when doing global routing, it adds by itself the pins and the vias

viali

(local interconnect <-> metal 1) over the available

li

area on each standard cell? (fig 1) I'm asking this because I was designing some cells but I was adding by myself the pins in the metal layer (fig 2) (obs: this cell was to find the Wpmax and Wnmin respecting DRC)

Check out interesting OpenROAD updates in 2022 and what lies ahead: https://theopenroadproject.org/openroad-2022-year-end-review/

@Matt Liberty Is Power Gate insertion flow is validated through openlane ? any MPW project with power gate ?

OpenROAD @OpenROAD_EDA projects are now available for summer internships via GSoC 23- https://lnkd.in/gHre-c3. Check them out -- we are now receiving proposals from qualified candidates. https://lnkd.in/g5cN7dHg

Hi, I am not sure if this is the best place for this so feel free to tell me to go elsewhere but I am having difficulty installing openroad from source on ubuntu 22.04. I am get an error during make that I am sure is due to a missing dependancy but I can't figure out what. It seems to have to do with boost but this is installed. Here is the snap shot of the log. Can rerun and get the whole log if need. Posted in #sky130

hello! i'm trying to install OpenROAD using OpenROAD-flow-scripts but there is an error

-- GPU is not enabled
CMake Error at src/mpl2/CMakeLists.txt:42 (find_package):
  By not providing "Findortools.cmake" in CMAKE_MODULE_PATH this project has
  asked CMake to find a package configuration file provided by "ortools", but
  CMake did not find one.
By not providing "Findortools.cmake" in CMAKE_MODULE_PATH this project has
  asked CMake to find a package configuration file provided by "ortools", but
  CMake did not find one.

  Could not find a package configuration file provided by "ortools" with any
  of the following names:

    ortoolsConfig.cmake
    ortools-config.cmake

  Add the installation prefix of "ortools" to CMAKE_PREFIX_PATH or set
  "ortools_DIR" to a directory containing one of the above files.  If
  "ortools" provides a separate development package or SDK, be sure it has
  been installed.

i can not find such package "ortools-config.cmake" to install. i would appreciate it if anyone could help

In my synthesis stage I get a bunch of warnings that look like

Warning: multiple conflicting drivers for CombinationalFFT.\v.comb_fft.genblk2[2].fft_stage.genblk1[3].bfu_in.dc [31]:
    port Y[31] of cell $techmap\v.comb_fft.genblk2[2].fft_stage.genblk1[3].bfu_in.$add$./designs/sky130hd/CombinationalFFT/CombinationalFFT__pickled.v:756$137 ($add)
    port Y[31] of cell $techmap\v.comb_fft.genblk2[2].fft_stage.genblk1[3].bfu_in.$add$./designs/sky130hd/CombinationalFFT/CombinationalFFT__pickled.v:757$138 ($add)

Then my OpenROAD crashes with the error in the picture, even though the module in the specified line looks like this:

module ButterflyVRTL (
	clk,
	reset,
	recv_val,
	recv_rdy,
	send_val,
	send_rdy,
	ar,
	ac,
	br,
	bc,
	wr,
	wc,
	cr,
	cc,
	dr,
	dc
);
	parameter n = 32;
	parameter d = 16;
	parameter mult = 1;
	input wire clk;
	input wire reset;
	input wire recv_val;
	input wire send_rdy;
	input wire [n - 1:0] ar;
	input wire [n - 1:0] ac;
	input wire [n - 1:0] br;
	input wire [n - 1:0] bc;
	input wire [n - 1:0] wr;
	input wire [n - 1:0] wc;
	output wire send_val;
	output wire recv_rdy;
	output wire [n - 1:0] cr;
	output wire [n - 1:0] cc;
	output wire [n - 1:0] dr;
	output wire [n - 1:0] dc;
	reg [n - 1:0] ar_reg;
	reg [n - 1:0] ac_reg;
	wire mul_rdy;
	wire [n - 1:0] tr;
	wire [n - 1:0] tc;
	FpcmultVRTL #(
		.n(n),
		.d(d)
	) mul(
		.clk(clk),
		.reset(reset),
		.ar(br),
		.ac(bc),
		.br(wr),
		.bc(wc),
		.cr(tr),
		.cc(tc),
		.recv_val(recv_val),
		.recv_rdy(recv_rdy),
		.send_val(send_val),
		.send_rdy(send_rdy)
	);
	always @(posedge clk)
		if (reset) begin
			ar_reg = 0;
			ac_reg = 0;
		end
		else if (recv_rdy) begin
			ar_reg = ar;
			ac_reg = ac;
		end
		else begin
			ar_reg = ar_reg;
			ac_reg = ac_reg;
		end
	




	always @(*) begin 
		cr = ar_reg + tr;
		cc = ac_reg + tc;

		dr = ar_reg - tr;
		dc = ac_reg - tc;
	end
endmodule

Any idea on how to fix this? Thank you so much in advance!

Also when I change the additions to bit shifts, the synthesis stage seems to run fine but the multiple constant driver warnings continue to appear.

is there any documentation on adding new standard cell libraries?

Hello! is .gds file generated by Align compatible with openfasoc?

Seize the Last Chance to Break Barriers: The OpenROAD 7nm Physical Design Contest The OpenROAD 7nm Physical Design Contest: Breaking Barriers with Open-Source VLSI has been a hot topic in the world of VLSI design. This is an opportunity for anyone to showcase their skills in designing and implementing physical designs using open-source tools. As the last day approaches for registration, it's important to emphasize the value of the last day and last opportunity. We often underestimate the power of last chance, but in reality, it can be the key to unlocking our potential and achieving success. The last day is a reminder that time is precious and should not be taken for granted. It's an opportunity to reflect on what we have accomplished so far and to evaluate what else we can achieve in the time remaining. This is particularly true for the OpenROAD 7nm Physical Design Contest, as this last day is the only chance to register and participate in this exciting competition. Last opportunities also allow us to push ourselves beyond our limits. When we know that there is no more time left, we tend to focus more on our goals and make the most of the opportunity presented to us. The OpenROAD 7nm Physical Design Contest is no exception, and it's a chance to break barriers and showcase our skills in open-source VLSI design. The last day is also a reminder that success is not about waiting for the perfect moment or perfect opportunity. Success is about taking action and making the most of every opportunity, even if it's the last one available. It's about putting in the hard work and dedication to achieve our goals. The OpenROAD 7nm Physical Design Contest is a unique opportunity to showcase our skills and make a mark in the world of VLSI design. It's a chance to work with like-minded individuals and push ourselves to the limits. The last day is a reminder that this opportunity will not come again, and we must seize it now. In conclusion, the last day and last opportunity are a valuable reminders of the importance of time, dedication, and seizing the moment. The OpenROAD 7nm Physical Design Contest is a great example of this, and it's an opportunity that shouldn't be missed. So if you haven't registered yet, take this last chance and make the most of it! Register using the below link: https://www.openroaddesigncontest.org/ Posted in #general

@Matt Liberty @Indira Iyer @Vijayan Krishnan OpenRoad team, Initially I thought my MPW-2 project will be dead on arrival. I am happy see Basic Boot working with my MPW-2 chip. I like to thank 🙏 openroad team for all the effort in creating, maintaining and continuously improving the openlane flow. I have created a short youtube video on my MPW-2 Project & Bring-up Status.

i would appreciate if anyone could help me with this error. i tried to change core and die areas but they don't work.

INFO GPL-0030] NumBins: 16
[ERROR GPL-0304] RePlAce diverged at initial iteration. Re-run with a smaller init_density_penalty value.
Error: global_place.tcl, 49 GPL-0304
Command exited with non-zero status 1
Elapsed time: 0:00.49[h:]min:sec. CPU time: user 0.45 sys 0.03 (98%). Peak memory: 99240KB.
make[1]: *** [Makefile:411: /home/milad/EDA/openfasoc/openfasoc/generators/my-design/flow/results/sky130hd/PLL//3_3_place_gp.odb] Error 1
make[1]: Leaving directory '/home/milad/EDA/openfasoc/openfasoc/generators/my-design/flow'
[Error] Placement failed. Refer to the log file
make: *** [Makefile:11: sky130hd_pll] Error 1

How can we use the Olimex ARM-USB-TINY-H debugger for Artix 7-35T Fpga board to debug a custom design ?

hello everyone i'd like to ask for help to solve (if it's needed) some warnings i got after installing openroad and making test. I'm worry about them because i don't know how to fix them and it looks like it'll be a problem can someone help me, please? thank you for your time!

@Vijayan Krishnan latest openlane flow is breaking in my Riscduino project at klayout GDS streaming out phase. Do we need to update any addition variable in config file ?

[ERROR]: during executing: "python3 /openlane/scripts/klayout/stream_out.py --output /home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/results/signoff/wb_interconnect.klayout.gds --lyt /opt/pdk_mpw9/sky130A/libs.tech/klayout/tech/sky130A.lyt --lym /opt/pdk_mpw9/sky130A/libs.tech/klayout/tech/sky130A.map --lyp /opt/pdk_mpw9/sky130A/libs.tech/klayout/tech/sky130A.lyp --top wb_interconnect --with-gds-file /opt/pdk_mpw9/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds --input-lef /home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/tmp/merged.nom.lef /home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/results/routing/wb_interconnect.def |& tee /dev/null /home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/wb_interconnect/runs/wb_interconnect/logs/signoff/32-gdsii-klayout.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
Warning: No mapping for layer 'pwell', purpose 'LEFOBS' - layer is ignored
'NoneType' object has no attribute 'cell_index'
child process exited abnormally

[ERROR]: Step(32:gds_klayout) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "try_exec" line 17)
    invoked from within
"try_exec python3 $::env(SCRIPTS_DIR)/klayout/stream_out.py --output $klayout_out --lyt $::env(KLAYOUT_TECH) --lym $::env(KLAYOUT_DEF_LAYER_MAP) --lyp ..."
    (procedure "run_klayout" line 22)
    invoked from within
"run_klayout"
    (procedure "run_klayout_step" line 3)
    invoked from within

Download and install pre-built

openroad

binary from here: https://github.com/Precision-Innovations/OpenROAD/actions/workflows/github-actions-build-deb-package.yml. Only support Ubuntu20.04/22.04 and Debian 10/11.

Hi, I am looking for the interpolation function used with NLDM in static timing analysis, will appreciate any help.

What is the status of latch-based timing analysis in OpenTimer and OpenSTA?

@Matt Liberty - is there power gating supported in openroad?

Hi, I'm kinda new to ORD so this question may have already been asked. When I launch detailed placement (i.e. OpenDP) from the Tcl interpreter, the tool crashes because of a segmentation fault in the initGrid function. Has anyone already encountered this problem / found a solution? I'll appreciate any help, thanks in advance

Hi, is there a way to obtain the HPWL estimation at any given PD step? By that I mean: when I run GPL, it prints the HPWL value (I'd say estimated given no routing has been done yet) for every iteration. Is there a way to obtain a report of such value after the elaboration is finished? Thanks in advance

Hi What the easiest way to get all buffers cells?

Excuse me, is there any mult-core acceleration support in Openroad? Openlane has option like ROUTING_CORE to accelerate its routing stage. Does Openroad has such kind of things?

十里的未来 has joined this channel by invitation from open-source-silicon.dev.

@Matt Liberty Is these a easy way to constrain the tool to place group of cells in small region with-in floor plan?. Background: I like control control clock skew cells near to PAD in each MACRO, but these cells are scattered in floor plan and it's creating different delay in each MACRO.

AWS uses OpenROAD for low-cost and easy access to IC design solutions on the cloud. Check out he blog here: https://aws.amazon.com/blogs/industries/open-source-chip-design-on-aws/