Hi,
we are doing post layout simulation for compar...
# analog-designs
Saranya P U
08/02/2024, 10:54 AMHi,
we are doing post layout simulation for comparator.But we are getting different outputs for schematic simulation and postlayout simulation.what could be the reason anyone please help.Attaching the spice files
l
Luis Henrique Rodovalho
08/02/2024, 11:40 AMIf this is a transient simulation and the post layout sims consider parasitic caps, then the results will differ. If you haven't tried it yet, extract the circuit for LVS, without any parasitics. Be sure that the pin order is right.
s
Saranya P U
08/02/2024, 11:43 AMwe tried simulating without the parasitic capaciatnces.but got same result.and in case of pin order how can we make the pins are in right order..
l
Luis Henrique Rodovalho
08/02/2024, 11:44 AMYou can inspect the spice files and see if the xschem netlist has the same pin order of the extracted netlist
Luis Henrique Rodovalho
08/02/2024, 11:47 AM Copy code
** sch_path: /home/user/Desktop/reram/september_tapeout/september_comparator/xschem/comaparator_post.sch
**.subckt comaparator_post
V1 in1 GND pulse(5 -5 0 1n 1n 100u 200u
V3 VDD GND 5
V2 vss GND -5
V4 vref GND 1
x1 VDD vss in1 vref Vout comparator Copy code
.subckt comparator VDD Vout vss in1 vref
XXM13 m1_1852_1814# m1_1852_1814# VDD VDD sky130_fd_pr__pfet_g5v0d10v5_KLAZY6
XXR5 m1_1646_n910# vss m1_2208_n248# sky130_fd_pr__res_xhigh_po_0p35_4SUKHP
XXM1 m1_2208_n248# vss vss m1_2208_n248# sky130_fd_pr__nfet_g5v0d10v5_UNEQ2N
XXM2 m1_3276_n836# vss vss m1_2208_n248# sky130_fd_pr__nfet_g5v0d10v5_UNEQ2N
XXM3 m1_3026_1786# vss vss m1_2208_n248# sky130_fd_pr__nfet_g5v0d10v5_UNEQ2N
XXM4 Vout vss vss m1_3026_1786# sky130_fd_pr__nfet_g5v0d10v5_UNEQ2N
XXM5 m1_1852_1814# vss m1_3276_n836# in1 sky130_fd_pr__nfet_g5v0d10v5_UNEQ2N
XXM6 m1_2443_1809# vss m1_3276_n836# vref sky130_fd_pr__nfet_g5v0d10v5_UNEQ2N
XXM7 m1_1852_1814# m1_2443_1809# VDD VDD sky130_fd_pr__pfet_g5v0d10v5_KLAZY6
XXM9 m1_3026_1786# Vout VDD VDD sky130_fd_pr__pfet_g5v0d10v5_KLAZY6
XXM8 m1_2443_1809# m1_3026_1786# VDD VDD sky130_fd_pr__pfet_g5v0d10v5_KLAZY6
XXC7 m1_3026_1786# m1_2443_1809# sky130_fd_pr__cap_mim_m3_1_FJFAMD
XXC8 XC8/m3_n386_n240# Vout sky130_fd_pr__cap_mim_m3_1_FJFAMD
XXM10 VDD vss m1_1646_n910# VDD sky130_fd_pr__nfet_g5v0d10v5_UNEQ2N
.endsLuis Henrique Rodovalho
08/02/2024, 11:48 AMCan you see it?
s
Saranya P U
08/02/2024, 11:50 AMYes. But how can we make it same.?
l
Luis Henrique Rodovalho
08/02/2024, 11:51 AMJust edit manually your netlists. There are smarter ways to do that, but I don't know.
Luis Henrique Rodovalho
08/02/2024, 11:52 AMYou can define the port order in Xschem symbols or Magic layouts. Xschem port order is easier. I couldn't tame Magic yet.
s
Saranya P U
08/02/2024, 12:06 PMOk. now it is working fine. Thank you.
t
Tim Edwards
08/02/2024, 1:17 PMMagic has a definite issue with failing to keep port order in a post-extraction netlist, which is a known issue that I have not had time to debug, although it is a high priority.
s
Saranya P U
08/05/2024, 5:58 AM@Tim Edwards We are aiming for next tapeout. We already completed some parts of our design in magic version 4.3.460. Do we upgrade our magic version , if it is required , to which version we need to upgrade.?
t
Tim Edwards
08/06/2024, 3:41 PMI just checked in a fix today. This fix is in the opencircuitdesign.com repository as magic version 8.3.488 and will update in the github mirror by tomorrow.
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