Good morning, I have a question about the generation of the PDN. How can I be sure that the macros have been properly connected to the power supply? The flow completes successfully, but if I look at the PDN log file, it seems that they haven't been connected.

I’m not sure what you mean by

caravel_user_project

vs

OpenLane

. By OpenLane do you mean

flow.tcl

? With

caravel_user_project

, you execute

make <cellname>

, and this runs a version of openlane specified in the

Makefile

. If this version of openlane is different from the version of openlane that you’re running

flow.tcl

, then you might get different results. It looks like you’re using the proprietary sram macros. Are you following the instructions here?

Yes, I followed those instructions, and I also had to make some modifications because following the basic tutorial step by step did not work. Then I adapted it to my design.

@Luca Martis I have not run any LVS on designs with abstracted memory. @Marwan Abbas Do you know who would be able to respond to this?

@Luca Martis what are the modifications you needed to make? @Mitch Bailey We'll need to discuss the LVS more, I'm not sure how it's planned to run.

For example I don't want to communicate through the Wishbone bus.

Okay, that shouldn't be a problem, the wishbone controller is just there as an example, it is also soft, so you don't have to use it.

But then, can these memories be used or not?

Yes, your issue is there because the memories are abstracted, we run LVS after the final integration of the actual commercial SRAM (in the tapeout flow). What I'm checking is the ability to run with the macro abstracted. But you should be fine and if we catch anything after integration you will be notified, our team is dedicated to make sure that the integration is correct and that your design doesn't have issues with the integration. Ofcourse I know you'd like to run LVS yourself and that's what I'm checking, I'll get back to you ASAP.

So, if I wanted to implement this module, for example, where four memories are used together, is there no way to know if it will work or not?

Do you have this on an efabless repo? can you give me access to it if you have the generated files uploaded it would be easier to assist you

@Marwan Abbas I just created it.

Can you please send us the URL?

@Anton Maurovic (efabless support) @Mitch Bailey we need to take a look at this please

Yes

This will make the LVS extract the lef file instead of the GDS, the SRAM GDS is actually empty because it's an abstract macro (because it's closed source) so when it tried to extract it, it doesn't find any cells, so it fails LVS.

Ok, and then what I expect to see ?

Yes, I just tried it on our example design and it passed LVS

Perfect, so the macro generated can be produced ?

Yes, in tapeout the SRAM that you see without cells now in your design will be replaced with the actual closed source SRAM macro before sending your design to the foundry

Perfect, thank you very much. Sorry for all the questions, but I have more. Were the coordinates I used for generating the obstructions correct?

No worries, you can ask as much as you want 🙂 I'm not sure about that one, but we can setup a call and review, I'll probably need to see a gds/lef file to be able to review that.

Of course, gladly. Would it be possible next week?

Sure thing! I'll send you a link to book a slot shortly.

Yes, of course. Right now, another design's flow is finishing. As soon as it's done, I'll send the one with the updated config file.

This is the link to book a slot with us https://info.efabless.com/meetings/marwan-abbas/chipignite-meeting

It seems that it didn't work.

@Luca Martis Can you share your full

lvs.report

file and the

lvs_config.json

file?

40-weights_mem.lvs.rpt

@Luca Martis thanks. The

lvs_config.json

file may be created when you run precheck. Looks like your results are from openlane’s LVS. The

lvs.rpt

file is just a summary. Can you share the full

39-SRAM_SRAM_1024x32_wb_wrapper.gds.lvs.log

file?

40-weights_mem.lef.lvs.log

@Luca Martis One thing I see is a layout port that does not exist in the verilog.

Subcircuit pins:
Circuit 1: EF_SRAM_1024x32                 |Circuit 2: EF_SRAM_1024x32                 
-------------------------------------------|-------------------------------------------
...
ScanOutCC                                  |(no matching pin)

Can you verify this on your side? Maybe check the

EF_SRAM_1024x32

lef versus the verilog stub. The sram power does not appear to be connected either.

Net: mem0/vnb                                                   
  EF_SRAM_1024x32/vnb = 1 
...

Can you share your

config.json

file?

Yes