Hello, I am trying to do an RTL sequential design. It has a clock and I added it in config.json. It shows The Network is combinational error at 1st step while hardening user_proj_example. It would be great to get suggestions in this regard. Here is the repo like for the code and log files: https://github.com/MdOmarFaruque/HW_For_AI_V2

@Md Omar Faruque I’m not sure, but your

CLOCK_NET

variable is set to

<http://counter.net|counter.net>

which I couldn’t find in your design. Do you need this variable? If it is not defined, it defaults to

CLOCK_PORT

, I think.

@Mitch Bailey Thank you for your reply. I deleted

CLOCK_NET

,still, it has the same error.

@Md Omar Faruque Could you push the latest results to the repo run directory?

Sorry about that.I have just done it

Looking at the synthesized gate level verilog here, you can see that the

clk

signal is unused. All connections to this signal have been optimized away. There are some other warnings in the synthesis logs that might be related.

Warning: Wire user_proj_example.\axi_rd_en is used but has no driver.
Warning: Wire user_proj_example.\intr is used but has no driver.
Warning: Wire user_proj_example.\digit [3] is used but has no driver.
Warning: Wire user_proj_example.\digit [2] is used but has no driver.
Warning: Wire user_proj_example.\digit [1] is used but has no driver.
Warning: Wire user_proj_example.\digit [0] is used but has no driver.

Does your rtl simulation work? Does it work even without the

clk

input?

Yes,the code worked fine in vivado.However,openlane showed error for 1st argument of readmemb().So I manually put all of the files instead of feeding filename from another module.besides,I used net type none at 1st and then net type wire at the last of user_proj_example That's what I modified.But yeah,at this point,I will consider running again then.

@Md Omar Faruque Maybe try asking on the #C016H8WJMBR channel about how to synthesize a design without a clock. I imagine it’s possible to simulate a design without a clock, but I don’t know about synthesis. This is not my area of expertise.

@Mitch Bailey But it has clock

Yes, but the clock does not effect the output, so it gets optimized out.

I am sorry. I know very little. Would you please explain why it gets optimized out?

I don’t know much more about verilog. Sorry.