Hi all. Is WPE modelled in this process? I havent ...
# sky130
d
Hi all. Is WPE modelled in this process? I havent extracted devices yet to see if the usual "sca/scb/scc" numbers are there. I presume it is but just confirming?
b
WPE is not modelled (WPEMOD=0 in the model files).
d
That's interesting. As these are essentially the same models as S130, I guess that means SW don't model WPE either? If so it would imply the effect is insignificant in this process. Ive worked on 180 processes where the foundry didnt model WPE due to its insignificance. Or is there another reason it isnt modeled? If it isnt insignificant, do we know any recommended safe distances from the well for this process (e.g. 2um is generally a good place to start)? Txs
b
I don't think it's insignificant. If you want the threshold voltages to match, they either need to have the same distance from the well edge or need to be several microns away. I remember 10um being a good number from the first paper on WPE. That said, I think foundries have worked to minimize WPE, so most commercial processes do better than that. No idea where things stand with SKY130. Matching the distances is what I'd do.
d
Thanks Boris. Yes I agree, matching distances is the safest approach to follow.
Following on from this discussion on proximity effects ... is LOD modelled in this process?
b
From what I can see, it's partially modeled in the BSIM4 files, e.g.
wkvth0
is defined, but on the other hand
lkvth0 = 0
. That said, magic does not seem to extract
SA
,
SB
,
SD
(someone should correct me if there is an option I haven't discovered), so the post-layout simulations will not not show any LOD effects.
d
That's interesting. I have passed the question onto the #magic channel to see if anyone knows about extracting these parameters. Thanks
Just to complete this thread - LOD is not modelled so best to keep at least 2um from the diffusion edge. From my experience with other foundries this is sufficient to keep LOD impact on id < 1%. But don't take my word as gospel, add margin e.g. I plan to T/O a chip in this process next year so will be keeping 5um from the edge!