Tiago Silva
08/06/2022, 2:47 AM[ERROR DRT-0305] Net one_ of signal type POWER is not routable by TritonRoute. Move to special nets.
Error: droute.tcl, 46 DRT-0305
child process exited abnormally
What could be causing this error?Arman Avetisyan
08/06/2022, 5:14 AMTiago Silva
08/06/2022, 2:34 PMmodule user_project_wrapper #(
parameter BITS = 32
) (
``ifdef USE_POWER_PINS`
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
``endif`
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
`input [MPRJ_IO_PADS-1:0] io_in,
`output [MPRJ_IO_PADS-1:0] io_out,
`output [MPRJ_IO_PADS-1:0] io_oeb,
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
`inout [MPRJ_IO_PADS-10:0] analog_io,
// Independent clock (on independent integer divider)
input user_clock2,
// User maskable interrupt signals
output [2:0] user_irq
);
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
bqmain bqmain0 (
``ifdef USE_POWER_PINS`
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
``endif`
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
// MGMT SoC Wishbone Slave
.wb_cyc_i(wbs_cyc_i),
.wb_stb_i(wbs_stb_i),
.wb_we_i(wbs_we_i),
.wb_adr_i(wbs_adr_i),
.wb_dat_i(wbs_dat_i),
.wb_ack_o(wbs_ack_o),
.wb_dat_o(wbs_dat_o),
.valid_i(1'b1),
.nreset(la_data_in[16]),
// IO Pads
.bq_clk_i(user_clock2),
.x(la_data_in[31:20]),
.y(la_data_out[11:0])
);
endmodule // user_project_wrapper
``default_nettype wire`
And the config:
set ::env(PDK) $::env(PDK)
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_project_wrapper
#section end
# User Configurations
## Source Verilog Files
set ::env(VERILOG_FILES) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
set ::env(CLOCK_PORT) "user_clock2"
#set ::env(CLOCK_NET) "mprj.clk"
set ::env(CLOCK_PERIOD) "20"
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_MACRO_HOOKS) "\
bqmain0 vccd1 vssd1 vccd1 vssd1"
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/biquad/bqmain.v"
set ::env(EXTRA_LEFS) "\
$script_dir/../../lef/bqmain.lef"
set ::env(EXTRA_GDS_FILES) "\
$script_dir/../../gds/bqmain.gds"
# set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
# disable pdn check nodes because it hangs with multiple power domains.
# any issue with pdn connections will be flagged with LVS so it is not a critical check.
set ::env(FP_PDN_CHECK_NODES) 0
# The following is because there are no std cells in the example wrapper project.
set ::env(SYNTH_TOP_LEVEL) 1
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
set ::env(FP_PDN_ENABLE_RAILS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0
Arman Avetisyan
08/06/2022, 8:44 PMArman Avetisyan
08/06/2022, 8:45 PMTiago Silva
08/06/2022, 8:57 PMset ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
Tiago Silva
08/06/2022, 9:21 PM.valid_i(1'b1),
It seems like this can't be done at the top level.Tiago Silva
08/06/2022, 9:21 PMBurak Aykenar
08/30/2022, 1:33 PMTiago Silva
08/30/2022, 2:01 PMArman Avetisyan
08/30/2022, 2:56 PMBurak Aykenar
09/05/2022, 8:48 AMVijayan Krishnan
09/05/2022, 9:04 AMBurak Aykenar
09/05/2022, 10:36 AMVijayan Krishnan
09/05/2022, 10:49 AMconfig.tcl
path?Burak Aykenar
09/05/2022, 10:54 AMVijayan Krishnan
09/05/2022, 11:02 AMBurak Aykenar
09/06/2022, 5:13 AMVijayan Krishnan
09/06/2022, 5:29 AMBurak Aykenar
09/06/2022, 6:16 AMVijayan Krishnan
09/06/2022, 6:23 AMVijayan Krishnan
09/06/2022, 6:28 AMOPENLAE_ROOT
for running wrapper will resolve this issue.
While running pre-check you may point mpw-7a tag for OPENLANE_ROOT
Burak Aykenar
09/06/2022, 6:35 AM