I'm having an issue when trying to make caravel user_project_wrapper during Detailed Routing.

[ERROR DRT-0305] Net one_ of signal type POWER is not routable by TritonRoute. Move to special nets.

Error: droute.tcl, 46 DRT-0305

child process exited abnormally

What could be causing this error?

provide the top level verilog and config. For some reason you have no tie high cells

Here is the top verilog:

module user_project_wrapper #(

parameter BITS = 32

) (

``ifdef USE_POWER_PINS`

inout vdda1,	// User area 1 3.3V supply

inout vdda2,	// User area 2 3.3V supply

inout vssa1,	// User area 1 analog ground

inout vssa2,	// User area 2 analog ground

inout vccd1,	// User area 1 1.8V supply

inout vccd2,	// User area 2 1.8v supply

inout vssd1,	// User area 1 digital ground

inout vssd2,	// User area 2 digital ground

``endif`

// Wishbone Slave ports (WB MI A)

input wb_clk_i,

input wb_rst_i,

input wbs_stb_i,

input wbs_cyc_i,

input wbs_we_i,

input [3:0] wbs_sel_i,

input [31:0] wbs_dat_i,

input [31:0] wbs_adr_i,

output wbs_ack_o,

output [31:0] wbs_dat_o,

// Logic Analyzer Signals

input  [127:0] la_data_in,

output [127:0] la_data_out,

input  [127:0] la_oenb,

// IOs

`input [

MPRJ_IO_PADS-1:0] io_in,

`output [

MPRJ_IO_PADS-1:0] io_out,

`output [

MPRJ_IO_PADS-1:0] io_oeb,

// Analog (direct connection to GPIO pad---use with caution)

// Note that analog I/O is not available on the 7 lowest-numbered

// GPIO pads, and so the analog_io indexing is offset from the

// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).

`inout [

MPRJ_IO_PADS-10:0] analog_io,

// Independent clock (on independent integer divider)

input   user_clock2,

// User maskable interrupt signals

output [2:0] user_irq

);

/*--------------------------------------*/

/* User project is instantiated  here   */

/*--------------------------------------*/

bqmain bqmain0 (

``ifdef USE_POWER_PINS`

.vccd1(vccd1),	// User area 1 1.8V power

.vssd1(vssd1),	// User area 1 digital ground

``endif`

.wb_clk_i(wb_clk_i),

.wb_rst_i(wb_rst_i),

// MGMT SoC Wishbone Slave

.wb_cyc_i(wbs_cyc_i),

.wb_stb_i(wbs_stb_i),

.wb_we_i(wbs_we_i),

.wb_adr_i(wbs_adr_i),

.wb_dat_i(wbs_dat_i),

.wb_ack_o(wbs_ack_o),

.wb_dat_o(wbs_dat_o),

.valid_i(1'b1),

.nreset(la_data_in[16]),

// IO Pads

.bq_clk_i(user_clock2),

.x(la_data_in[31:20]),

.y(la_data_out[11:0])

);

endmodule	// user_project_wrapper

``default_nettype wire` And the config:

set ::env(PDK) $::env(PDK)

set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"

# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS

source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl

# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL

source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl

set script_dir [file dirname [file normalize [info script]]]

set ::env(DESIGN_NAME) user_project_wrapper

#section end

# User Configurations

## Source Verilog Files

set ::env(VERILOG_FILES) "\

$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \

$script_dir/../../verilog/rtl/user_project_wrapper.v"

## Clock configurations

set ::env(CLOCK_PORT) "user_clock2"

#set ::env(CLOCK_NET) "mprj.clk"

set ::env(CLOCK_PERIOD) "20"

## Internal Macros

### Macro PDN Connections

set ::env(FP_PDN_MACRO_HOOKS) "\

bqmain0 vccd1 vssd1 vccd1 vssd1"

### Macro Placement

set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg

### Black-box verilog and views

set ::env(VERILOG_FILES_BLACKBOX) "\

$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \

$script_dir/../../verilog/rtl/biquad/bqmain.v"

set ::env(EXTRA_LEFS) "\

$script_dir/../../lef/bqmain.lef"

set ::env(EXTRA_GDS_FILES) "\

$script_dir/../../gds/bqmain.gds"

# set ::env(GLB_RT_MAXLAYER) 5

set ::env(RT_MAX_LAYER) {met4}

# disable pdn check nodes because it hangs with multiple power domains.

# any issue with pdn connections will be flagged with LVS so it is not a critical check.

set ::env(FP_PDN_CHECK_NODES) 0

# The following is because there are no std cells in the example wrapper project.

set ::env(SYNTH_TOP_LEVEL) 1

set ::env(PL_RANDOM_GLB_PLACEMENT) 1

set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0

set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0

set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0

set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0

set ::env(FP_PDN_ENABLE_RAILS) 0

set ::env(DIODE_INSERTION_STRATEGY) 0

set ::env(FILL_INSERTION) 0

set ::env(TAP_DECAP_INSERTION) 0

set ::env(CLOCK_TREE_SYNTH) 0

You dont have SYNTH_USE_PG_PINS_DEFINES defined

Those are already defined in the fixed configs of caravel as follows:

set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]

set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]

set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"

hi @Tiago Silva I got the same error how did you solve it? I can't understand why .valid_i(1'b1) cause this error?

The problem is the 1'b1. You can't assign 0s or 1s at the top level. This logic must be done inside the modules.

The tie cells are cells that need to be placed. Without tie cells it will give you and ESD issue because VDD will rise way above allowed gate voltage and will break the gate of the input transistors. One way is to create the cells manually, connect and use the same macro flow to place them.

thanks, I found a github issue about it: https://github.com/The-OpenROAD-Project/OpenLane/issues/1185 @Vijayan Krishnan now I deleted all direct assignment to '0' or '1' to any port or signal. This time I got error in "Detailed Routing" stage "Net zero_ of signal type GROUND is not routable by TritonRoute. Move to special nets" In my top module (user_project_wrapper) now I only have hardened macros, their connections and some assignments, which are assigned to wb_rst_i There are some empty output ports in instantiation of macros such as: ... .abc_signal_o(), ... does this cause problem? thanks

May i know the OpenLane version currently using?

it is e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066 actually it is caravel user project mpw7 tag openlane version however I updated sky130B pdk due to some errors with mpw7 sky130B pdk version

e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066 with this commit, tie cell features already there. it should not throw that routing error. Can you share your repo link and

config.tcl

path?

yes thanks for your help https://github.com/mbaykenar/mpw7_yonga_soc/blob/main/openlane/user_project_wrapper/config.tcl https://github.com/mbaykenar/mpw7_yonga_soc

its need to be traced from netlist and def file. file github issue with reproducible test case. we will look into that.

ok thanks i issued https://github.com/The-OpenROAD-Project/OpenLane/issues/1320

its confusing b/w the commit ID mentioned in our thread, github issue.

I added these lines after initialize_floorplan in floorplan.tcl as stated in issue#1185 and issue#1002 and it passed at least Detailed Routing stage: set tielo_cell [lindex $::env(SYNTH_TIELO_PORT) 0] set tielo_port [lindex $::env(SYNTH_TIELO_PORT) 1] set tiehi_cell [lindex $::env(SYNTH_TIEHI_PORT) 0] set tiehi_port [lindex $::env(SYNTH_TIEHI_PORT) 1] insert_tiecells "$tielo_cell/$tielo_port" -prefix "TIE_ZERO_" insert_tiecells "$tiehi_cell/$tiehi_port" -prefix "TIE_ONE_"

Its good to know. I thought of suggesting same👍

actually I tried it but there are differences in configuration parameters, also in check scripts some editing also needed. I will continue with mpw openlane version and try to finish the flow hopefully for now