Hi , my design is failing in detailed routing step...
# openlaner
Ryan R
08/05/2022, 2:52 PMHi , my design is failing in detailed routing step.. Logfile doesnt seem to contain info for debug:
[INFO]: Running Global Routing...
[INFO]: Starting FastRoute Antenna Repair Iterations...
[STEP 19]
[INFO]: Running Fill Insertion...
[STEP 20]
[INFO]: Writing Verilog...
[STEP 21]
[INFO]: Running Detailed Routing...
[ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl
[ERROR]: Exit code: 1
[ERROR]: full log: designs/counter/runs/RUN_2022.08.05_14.23.00/logs/routing/21-detailed.log
[ERROR]: Last 10 lines:
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 308 vertical wires in 15 frboxes and 215 horizontal wires in 15 frboxes.
[INFO DRT-0186] Done with 8 vertical wires in 15 frboxes and 24 horizontal wires in 15 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 000352, elapsed time = 000206, memory = 9151.66 (MB), peak = 11359.00 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 000000, elapsed time = 000000, memory = 9151.72 (MB), peak = 11359.00 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
child killed: kill signal
[INFO]: Saving runtime environment...
[INFO]: Creating reproducible...
How can i log a case ? I forgot the steps
a
Arman Avetisyan
08/05/2022, 2:59 PMHow much memory (ram and swap) do you have? Is it running out of memory?
Arman Avetisyan
08/05/2022, 2:59 PM2. Whats density values, etc.
Need more information. At least give config.tcl and the area usage
r
Ryan R
08/05/2022, 3:16 PM# Design
set ::env(DESIGN_NAME) "counter"
set ::env(VERILOG_FILES) [glob ./designs/counter/src/*.v]
set ::env(CLOCK_PERIOD) "10.000"
set ::env(CLOCK_PORT) "clk"
set ::env(CELL_PAD) 4
set ::env(DIE_AREA) {0 0 5000 5000}
set ::env(FP_SIZING) absolute
set ::env(FP_CORE_UTIL) {30}
# set ::env(FP_PIN_ORDER_CFG) $::env(OPENLANE_ROOT)/designs/counter/pin_order.cfg
set filename ./designs/$::env(DESIGN_NAME)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
Ryan R
08/05/2022, 3:16 PMI have set UTIL of 30 -- i dont get any memory issue though.. Still how to check swap memory
a
Arman Avetisyan
08/05/2022, 3:39 PM5mm x 5mm is probably too much area. Thats why it runs out of memory
Arman Avetisyan
08/05/2022, 3:40 PMfp core util is ignored in absolute fp size
r
Ryan R
08/05/2022, 3:43 PMI commented these vars :
# Design
set ::env(DESIGN_NAME) "counter"
set ::env(VERILOG_FILES) [glob ./designs/counter/src/*.v]
set ::env(CLOCK_PERIOD) "10.000"
set ::env(CLOCK_PORT) "clk"
set ::env(CELL_PAD) 4
#set ::env(DIE_AREA) {0 0 100 100}
#set ::env(FP_SIZING) absolute
#set ::env(FP_CORE_UTIL) {30}
# set ::env(FP_PIN_ORDER_CFG) $::env(OPENLANE_ROOT)/designs/counter/pin_order.cfg
set filename ./designs/$::env(DESIGN_NAME)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
Ryan R
08/05/2022, 3:44 PMnow it crashes earlier ---
Ryan R
08/05/2022, 3:44 PMSTEP 2]
[INFO]: Running Single-Corner Static Timing Analysis...
[STEP 3]
[INFO]: Running Initial Floorplanning...
[WARNING]: Current core area is too small for a power grid. The power grid will be minimized.
[INFO]: Setting Core Dimensions...
[STEP 4]
[INFO]: Running IO Placement...
[STEP 5]
[INFO]: Running Tap/Decap Insertion...
[INFO]: Power planning with power {VPWR} and ground {VGND}...
[STEP 6]
[INFO]: Generating PDN...
[STEP 7]
[INFO]: Running Global Placement...
[ERROR]: during executing openroad script /openlane/scripts/openroad/replace.tcl
[ERROR]: Exit code: 1
[ERROR]: full log: designs/counter/runs/RUN_2022.08.05_15.43.08/logs/placement/7-global.log
[ERROR]: Last 10 lines:
[INFO GPL-0070] 0.5rcK: 1.0
[INFO GPL-0071] 1.0rcK: 1.0
[INFO GPL-0072] 2.0rcK: 0.0
[INFO GPL-0073] 5.0rcK: 0.0
[INFO GPL-0074] FinalRC: 0.95
[INFO GPL-0100] worst slack 6.57e-09
[INFO GPL-0103] Weighted 1 nets.
[ERROR GPL-0306] RePlAce diverged at wire/density gradient Sum.
Error: replace.tcl, 91 GPL-0306
child process exited abnormally
[INFO]: Saving runtime environment...
[INFO]: Creating reproducible...
Ryan R
08/05/2022, 4:20 PMRyan R
08/05/2022, 4:20 PMlooks like this is recent bug
a
Arman Avetisyan
08/05/2022, 4:28 PMits small and you are using 5mm x 5mm?
If it small then set the size to 300um x 300um
r
Ryan R
08/05/2022, 4:28 PMi set as 100um and 100um , seems ok with the hack variable as in the issue
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