Does anyone know if this is implemented in chip? The register has no impact on PLL , register pll divider. Also the pll source how does it work? I tried how @Matt Venn showed in webinar but it seems not to work linearly. It’s jumping only two values if I monitor gpio blink code as pll varies .

@tim, this one is for you.

This is a feedback divider, not an output divider. If the value of the feedback divider times the input clock frequency is not within the range of the DLL (which is about 50 to 100MHz), then you can only get one of two values---Either the DLL rails at the highest frequency/lowest trim (about 100MHz) or at the lowest frequency/highest trim (about 50MHz). If you run the DLL in DCO mode (not locked to anything), then you can apply the trim value manually and see the frequency change according to the trim value.