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Hello everyone here, I am newbie using the open source tool OPEN-ROAD for RTL TO GDS||. While reading the Netlist generated from the yosys it throws syntax error also when i am trying to read design file. It also throws the same error. Can anyone guide me how to fix this. I have simulated the code on other tool and has no error. 

For those who can look into this issue, the verilog files are available here. <https://open-source-silicon.slack.com/archives/C032VUYLL64/p1717430620270409?thread_ts=1717429760.158529&amp;cid=C032VUYLL64>

These are not structural netlists. OpenROAD only works with techmapped, structural netlists.

OpenSTA works with behavioral verilog (I believe) but you would have to use the standalone module

These files could not have been generated from yosys, or if they were, yosys was not run properly.

could you please let me know what is the command for generating structural netlis

I would recommend using a flow like OpenROAD-flow-scripts or OpenLane. The whole yosys script is responsible for RTL parsing and netlist generation.