Hello, we're having trouble with the DRC check on our design. Switching from drc(fast) to drc(full) makes 17846 DRC errors show up, and

drc why

only reports the following

% drc why

MiM cap bottom plate spacing < 1.2um (capm.2b)

Running

drc count

seems to indicate no actual errors:

% drc count

Cell user_analog_project_wrapper has 17846 error tiles.

Total DRC errors found: 0

These error tiles follow a diagonal pattern all across our PMOS and NMOS waffles, shown in the picture that was included. We do have MiM caps near this subcell, but they do not seem to break this rule, and running

drc check

with drc(full) on the area that contains them does not generate DRC errors. Using

drc find capm.2b

doesn't seem to actually find anything specific. Is the capm.2b DRC error causing all of these error tiles, and why does it not show as a DRC error in count?

It's a bit hard to see TBH. Can you post the mag file (or just a copy of just the problematic part) ?

@Francisco Aguirre my understanding is that the bottom plate metal spacing rule is not actually about metal Rather than check the via spacing, wider metal spacing is required instead. That said, a solution may be to modify the layout to reduce what is considered as cap bottom metal. If you have a direct metal connection to the cap bottom metal, All that metal may be considered cap bottom metal. Connecting to cap top metal instead or adding a change in metal layer would limit the extent of the layer being checked.