I'm reading some thing about CDR and how to implement clock recovery, more specifically the "Bang Bang" method. I quickly made a VCO (current starved) schematic and that can definitely provide a a frequency of my data source but the range of frequency it can do is fairly wide, including very far from the data frequency, so although I can see how the bang bang method can "keep track" of the alignement and tweak the VCO to stay in lock, I'm a bit more dubious about its ability to acquire a lock at the right frequency in the first place.
Are you supposed to somehow first bring the VCO to close to the expected data rate "somehow" ? And have some secondary control voltage ?