open-source-silicon.dev

Hello all, I'm running into some FEOL DRC failures on an openlane 2 generated shift registers, specifically minimum PSDM spacing in periphery problems between tap cells and their adjacent standard cells. Does anyone have any ideas on this?

I was able to  fix 1 out of the 2 DRCs simply by deleting the adjacent Fill cell next to the tap, but the other problem occurs between a tap and an adjacent mux so I cannot manually go in and fix it

<https://colab.research.google.com/drive/1TY8O6sfi4S2rgk64_XWUf7OcoMM6cy5Q?usp=sharing>

Here is the notebook that generated the shift registers.  It is clean in the openlane2 flow, but encounters the FEOL DRC failure in the precheck.

What is Linen?