hi, while i was hardening my design i got following error. How can we resolve this error? Thanks inadvance

[INFO]: Run Directory: /openlane/designs/Top/runs/RUN_2024.05.31_10.48.17
[INFO]: Saving runtime environment...
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[INFO]: Running linter (Verilator) (log: designs/Top/runs/RUN_2024.05.31_10.48.17/logs/synthesis/linter.log)...
[INFO]: 0 errors found by linter
[WARNING]: 17 warnings found by linter
[INFO]: Running Synthesis (log: designs/Top/runs/RUN_2024.05.31_10.48.17/logs/synthesis/1-synthesis.log)...
[INFO]: Running Single-Corner Static Timing Analysis (log: designs/Top/runs/RUN_2024.05.31_10.48.17/logs/synthesis/2-sta.log)...
[INFO]: Running Initial Floorplanning (log: designs/Top/runs/RUN_2024.05.31_10.48.17/logs/floorplan/3-initial_fp.log)...
[WARNING]: Current core area is too small for the power grid settings chosen. The power grid will be scaled down.
[INFO]: Floorplanned with width 16.56 and height 16.32.
[INFO]: Running IO Placement (log: designs/Top/runs/RUN_2024.05.31_10.48.17/logs/floorplan/4-place_io.log)...
[INFO]: Running Tap/Decap Insertion (log: designs/Top/runs/RUN_2024.05.31_10.48.17/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {VPWR} and ground {VGND}...
[INFO]: Generating PDN (log: designs/Top/runs/RUN_2024.05.31_10.48.17/logs/floorplan/6-pdn.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl
[ERROR]: Log: designs/Top/runs/RUN_2024.05.31_10.48.17/logs/floorplan/6-pdn.log
[ERROR]: Last 10 lines:
Using 1e+03 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-09 for power...
Using 1e-06 for distance...
Reading design constraints file at '/openlane/designs/Top/runs/RUN_2024.05.31_10.48.17/tmp/floorplan/3-initial_fp.sdc'…
[ERROR PDN-0175] Pitch 4.1400 is too small for, must be atleast 6.6000
Error: pdn_cfg.tcl, 92 PDN-0175
child process exited abnormally

[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...
[INFO]: Reproducible packaged: Please tarball and upload 'designs/Top/runs/RUN_2024.05.31_10.48.17/issue_reproducible' if you're going to submit an issue.
[ERROR]: Step 6 (floorplan) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_tcl_script" line 219)
    invoked from within
"run_tcl_script -tool openroad -no_consume {*}$args"
    (procedure "run_openroad_script" line 2)
    invoked from within
"run_openroad_script $::env(SCRIPTS_DIR)/openroad/pdn.tcl  -indexed_log [index_file $::env(floorplan_logs)/pdn.log]  -save "to=$::env(floorplan_results..."
    (procedure "gen_pdn" line 15)
    invoked from within
"gen_pdn"
    (procedure "run_power_grid_generation" line 65)
    invoked from within
"run_power_grid_generation"
    (procedure "run_floorplan" line 56)
    invoked from within
"run_floorplan"} -errorline 1
[INFO]: Saving current set of views in 'designs/Top/runs/RUN_2024.05.31_10.48.17/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'designs/Top/runs/RUN_2024.05.31_10.48.17/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'designs/Top/runs/RUN_2024.05.31_10.48.17/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.
[INFO]: The failure may have been because of the following warnings:

Looks like the synthesized cell may be too small for the power grid. Can you try specifying a larger absolute size in the config.json file?

thanks @Mitch Bailey I not have that much knowledge about varying config parameters. I used default config.json file with only changing design name, source verilog files and pin config file. Can you please elaborate how to do that? I just attaching my config.json file below.

{
  "DESIGN_NAME": "Top",
  "VERILOG_FILES": "dir::src/*.v",
  "CLOCK_PERIOD": 10,
  "CLOCK_PORT": "clk",
  "CLOCK_NET": "ref::$CLOCK_PORT",
  "FP_PDN_VOFFSET": 7,
  "FP_PDN_HOFFSET": 7,
  "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
  "FP_PDN_SKIPTRIM": true,
  "pdk::sky130*": {
    "FP_CORE_UTIL": 45,
    "scl::sky130_fd_sc_hd": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hdll": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hs": {
      "CLOCK_PERIOD": 8
    },
    "scl::sky130_fd_sc_ls": {
      "CLOCK_PERIOD": 10,
      "MAX_FANOUT_CONSTRAINT": 5
    },
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  },
  "pdk::gf180mcu*": {
    "CLOCK_PERIOD": 24,
    "FP_CORE_UTIL": 40,
    "MAX_FANOUT_CONSTRAINT": 4,
    "PL_TARGET_DENSITY": 0.5
  }
}

@Allwan S Anand See https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/reference/configuration.md

"FP_SIZING": "absolute",
"DIE_AREA": "0 0 400 400",

maybe.