Hi all, I'm working on understanding the flow of s...
# openlane
h
Hi all, I'm working on understanding the flow of synthesis, using OpenROAD and the using KLayout using OFRS. I've taken the YoSys synthesis output from https://github.com/OuDret/OnlyNandYosysSynth/tree/main/OnlyNandYosysSynth/output and am trying to smoke tests one of the gate-level netlist results using this guide. However, I continually get errors like this. May I know if this smoke test requires more than just the gate-level netlist Verilog file or can the flow just run using it? I'm super new to this and help would be greatly appreciated.
m
@H'Ng Wei Dan maybe you mean ORFS (openroad flow script)? This is the #openlane channel and even though both openlane and ORFS convert rtl verilog to GDS and both use openroad, they are maintained by 2 separate groups. I couldn’t find an #ORFS channel, but you might try asking on the #openroad channel.
h
Alright thanks!