Hi, can I get some help? Currently I'm layouting 12-Bit Current Mode DAC for Chipalooza Challenge using Magic VLSI. I have some issue in LVS. This problem appear in the digital part, especially in logic gate standard cells. I think my layout is connected properly as in the schematic, but i've got some netlist mismatch. Below here I provided the spice and comp.out file. icell1scs_sch.spice was is the schematic spice and icell1scs_lay2.spice from the layout. To test, I create a dummy project that consists of 1 and gate standard cell, and try to compare it with the layout from sky130 standard cells. And I get the same problem from Netgen LVS, netlist mismatch. Do I miss something while I create the layout? Do I need to create some port or label, or some config in tcl file? I've tried many things that I found on the Internet but none of them worked. I attach all my screenshoot of my project below. Please let me know the solution. Thank you very much🙂

Hi @Yohanes Stefanus Thanks for your participation in open source silicon! Hopefully, we can relieve some of your frustration (just noticed that “relieve” missing an “e” is “relive” - we want to avoid that.) 1. I suggest adding layout ports to the top level. Currently, your comparing a layout without ports

.subckt icell1scs_lay2

to a schematic with ports

.subckt icell1scs iout avdd pbias ioutn sw pcbias idir_sel ncbias nbias avss

2. LVS results are much easier to analyze if the layout and schematic have the same names. I suggest dropping the

_lay*

suffices from the layout cells so that they match the schematic. 3. Along with the lvs results that you’ve shared, it is helpful if you share the actual command that you used to run netgen. 4. The schematic netlist references the standard cells, but they are not defined. You could include

$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice

in the spice file, but I prefer to do it when I run netgen. I use a script (let’s call it

lvs.script

) like this

set layout [readnet spice icell1scs_lay2.spice]
set source [readnet spice $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice]
readnet spice icell1scs_sch.spice $source
lvs "$layout icell1scs" "$source icell1scs" $::env(PDK_ROOT)/$::env(PDK)/libs.tech/netgen/$::env(PDK)_setup.tcl

and then run netgen with

netgen -batch source lvs.script

Thank you for replying! I use

netgen lvs "icell1scs_lay2.spice icell1scs_lay2" "icell1scs_sch.spice icell1scs"

command to run the lvs. I run netgen in tckon panel from the magic. And I use

extract all

,

ext2spice lvs

,

ext2spice

to get spice file from the layout. I've tried your script too, and I got this message

yohanes@yohanes-HP-Laptop-14s-fq1xxx:~/gits/dsrt_2024/sky130_its_ip__idac3v_12bit/magic$ netgen -batch source lvs.script 
Netgen 1.5.272 compiled on Jum 29 Mar 2024 12:02:55  WIB
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Call to undefined subcircuit sky130_fd_pr__nfet_g5v0d10v5
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__pfet_g5v0d10v5
Creating placeholder cell definition.
no such variable
    (read trace on "::env(PDK_ROOT)")
    invoked from within
"readnet spice $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice"
    (file "lvs.script" line 2)
    invoked from within
"source lvs.script"
    ("eval" body line 1)
    invoked from within
"eval $argv"

@Yohanes Stefanus Sorry about that. I was sort of guessing at the tcl syntax. Do you have PDK_ROOT and PDK set in your environment?

env | grep PDK

If not, try setting them first.

sorry for very late respone, I just check my slack again. I already solve those problem by import the spice file from schematic to layout. So I don't need to make the transistor from scratch. This also make my layout free from netlist mismatch. However, sometimes I still got port errors even the circuits are match uniquely. Is it okay?

@Yohanes Stefanus port errors will probably cause problems at higher hierarchies. I suggest you fix them. They some times result from the swapping of NAND/NOR inputs. Our LVS setup does not (generally) allow permutability.