Hi everyone - Does anyone know what the minimum pad size we can do in sky130? How small can we draw pad openings and what would be the minimum pitch between pad openings. I saw this: • https://open-source-silicon.slack.com/archives/C01EX4ATEKF/p1705608474644549 but the 70x60um is for wiring bonding and I am sure we can make smaller pad openings ... I looked here: • https://skywater-pdk.readthedocs.io/en/main/rules/assumptions.html#process-stack-diagram but had trouble figuring out which rule is the right rule to answer this question. Any thoughts?

There is a rule for minimum spacing between glass cut areas but no rule for pad size other than a general (but not enforced) requirement to use the official pad cells (which are 70 x 60). There are two "probe" standard cells in the HD set which bring the output and power supplies up to metal 5 for probing, but they do not have a glass cut layer and look like they may be designed with the intention of either etching off the nitride or not adding the final nitride. For other similar processes, the rule I recall (and this is from a long time back, and my recollection is rather fuzzy) is 15um, which is fairly consistent with the minimum 45 degree chamfer length of 7um (45 degree chamfers are required, another rule that is not enforced that I am aware of). If you want to be absolutely sure you're following all the right rules and recommendations, then stick with the 70x60 pad. Otherwise, it's all going to be guesswork.

Hi Tim -- thank you for this info! The Cornell Custom Silicon Systems (C2S2) project team is exploring a collaboration with HackerFab@CMU (https://hackerfab.ece.cmu.edu). C2S2 is thinking of taping out a sea-of-gates style chip through efabless/chipignite and then HackerFab@CMU would use their maskless-litho process to do two final layers of metal deposition on top. The idea is to enable students to manufacture interesting small projects in silicon but with very rapid turn around time. Seems kind of crazy but also super exciting. So we definitely want to try to push the limits on the minimum pad size to be able to get more transistors available to wire up via the HackerFab@CMU metal interconnect. I think this is the probe cell you were referring to? • https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/tree/main/cells/probe_p I just took a look at the GDS. It looks like the M5 in that cell is ~3x1.6um but I agree at least in the cell I don't see any glass cut so I am not sure how they are supposed to be used? I seem to remember some other efabless/chipignite tapeout with a bunch of analog probe points ... I wonder how big those probe points were? Any advice or thoughts would be greatly appreciated!

@mehdi had a hand in the test chip for NIST and can probably tell you what the pad size was. I think they were full-sized pads. Otherwise, we could probably track down a SkyWater engineer (@Andrew Wright: Who would be best to ask?).

Perfect. I will reach out @mehdi but if you have a contact at SkyWater that could provide some advice that would also be great!

@Christopher Batten Hi! You can use as small as 40umx40um. Here are a couple examples: https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/mpw-6 https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/Nanofab

Awesome! Any reason we cannot go smaller?

The limitation was on the probes. We went as small as 60um pitch for some structures. 80um in general.

ok! For this application we are not going to be probing but actually trying to deposit metal on top of the chip to connect these contacts to enable a kind of rapid sea-of-gates approach for teaching ... any thoughts on if there are practical limits to how small we can go if we are not limited by the probing side?

Ah.. I understand, you can use nanofab terminals which can be smaller 20x20 and maybe smaller. We have examples here: https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/Nanofab You are probably sacrificing the top layer? (I am on my phone right now) but I ll check later what the smallest sizes used. You can probably have smaller terminals.

Awesome ... any advice or thoughts you have would be greatly appreciated ... this is not urgent 🙂

Sure. All tiles here: https://github.com/idea-fasoc/openfasoc-tapeouts/tree/main/Nanofab%2Ftiles

ok! i just checked CV_tile_231120.gds and it seems to use 40x40um pads though? I also checked Cryo_tile_231203_1649.gds and it seems to have even larger 120x120um pads? Maybe I am not looking in the right place?

Ok, will send you a screenshot later. They are really smaller terminals.

Ah ha! I think I see now ... I went into cv_simple_top_231009.gds and I see the big 40x40 pads but I also see the much smaller 10x10um pads ... so for the 10x10pads do was there glass cut on top? I mean was the M5 exposed at the top-level the chip? Super cool .. so neat we can exchange and discuss this kind of stuff in an open-forum ... yay for open PDKs 🙂

Agreed! Are you doing nanofabrication/post fabrication? In our case we stop the process at the top layer -1. And the postfab on top of metal 4 in this case

plan is to have the students at HackerFab@CMU try depositing metal on top ... but eventually would love to do something similar in our Cornell Nanofabrication Facility clean room ... how did you get Skywater to stop the process at the top layer -1? Were you doing your own wafer as opposed to going through an efabless MPW?

Yes, it is a project with NIST where we use the whole wafer. Do you know Rick Carley at CMU? He is doing something similar to what you are doing.

No - I don't know Rick ... I will send him an email -- thanks for the lead!

All the best :)