I am modeling some opamps that are sensitive to leakage and capacitance. Planning to use the “straight-through” analog pins and the analog_io pins. Following the attached post, I have grabbed the sky130_ef_io__analog_minesd_pad_short spice models from sky130_ef_io__analog.spice. By adding 2pF, we have a good model for pin + package capacitance for (barely) ESD protected analog pins. However, I can't seem to find the

sky130_ef_io__esd_pdiode_11v0_single

devices (from the post) or 11V diodes (from the spice netlist) in xschem. Where can these be found? Are we able to use these directly in our designs? Next, I would like to model the analog_io pads that route through 150ohm resistor + ESD on the GPIO pads. There are quite a few subcircuits in sky130_fd_io.spice, but it is not clear which one models the analog_io behavior. There are a lot of discussions about leakage from a DCDC converter a few months ago, but no hard numbers or simulation methods. (Netlist for the minimal esd pads)

*---------------------------------------------------------------------------
* sky130_ef_io__analog_minesd_pad_short:
*---------------------------------------------------------------------------
* Simple pad, straight through, with ESD diodes (1 each P and N).
* All busses except for VDDIO and VSSIO removed
*---------------------------------------------------------------------------

.subckt sky130_ef_io__analog_minesd_pad_short P_CORE VDDIO VSSIO P_PAD
R0 P_PAD P_CORE sky130_fd_pr__res_generic_m5 w=253 l=0.1

D0 VSSIO P_CORE sky130_fd_pr__diode_pw2nd_11v0 pj=1.02e+08 area=5e+13
D1 P_CORE VDDIO sky130_fd_pr__diode_pd2nw_11v0 pj=1.02e+08 area=5e+13
.ends

@Vladimir Vesely: The

sky130_ef_io__esd_pdiode_11v0_single

is a layout cell, not a device. If you extract the layout, it is just an 11V diode. The "ESD" in the name implies things about the layout but SkyWater doesn't have a specific device model for an ESD diode vs. a regular diode.

Thanks for the tip. I will use the standard 11V diode. What is preventing me from copying the schematic of, say,

sky130_ef_io__analog_esd_pad

? I would like to have reasonable ESD protection on the analog pads. An existing layout would be great, but I would rather be able to use the full pad-frame. Would I need to extract the whole pad layout to estimate parasitics and leakage? I have seen some estimates of ~2pF on the analog_io, but would like to see a spice model if possible. I have poked around in

sky130_fd_io.spice

, but it is not clear if there is a good model for the analog_io pad configuration.

There is nothing preventing you from copying the netlist of the existing analog pads (although there are no schematics, per se). And yes, you could use the ESD structures from the analog pads to provide some ESD protection between your user project and the bare analog pads on Caravan. It will not be especially good ESD protection because it will not be directly under the pad to shunt current through the shortest path to the supply rails. But it's far better than nothing. However---I am not sure how good the diode models are, so I am not sure how accurate the simulation of leakage is going to be.

Cool, so looks like I will just do some basic ESD on analog_io. For gpio_analog (the previously mentioned 150ohm resistor), I suppose using the 2.7nA leakage current may suffice for my modeling. https://open-source-silicon.slack.com/archives/C031R263TC7/p1702586825511069?thread_ts=1701870862.658749&cid=C031R263TC7