Hi, we have a problem with the IO.3a2 drc rule. We have a big pmos transistor with drain connected to a asig_5p0 pad. It's required that the external PCOMP guardring should be at 15u max from the transistor PCOMP. The original design was 15u away from the COMP, but not from the diff layer (upper right box ruler). Then we added an extra guard ring surface because we think that the rule requires to be "less than 15um" (bottom left box ruler). This makes the drc error area to shrink which I think it's a bit conterintuitive if the idea is to add more distance between the transistors and the GR. What should we do to fix this error? Could the distance to diff also be considered on this rule? @Jorge Marin @Sebastian Sanchez @Tim Edwards @Juan Sebastian Moya @Mitch Bailey

IO.3a2 requires pcomp connected to pad to be within 15um of a ptap guard ring. I think your pfet array is too big to be within 15um of ptap guard ring.

That means no big fet should be connected directly to a pad? Or maybe a very large one

@aquiles viza

Maybe we could add an intermediate element that fits in the restriction and allow us to take part of the current outside

That’s what I was thinking. Maybe a short ndiffusion resistor? The resistor would need a double guard ring. However, I doubt that there’s is any chance of latchup because there is no active ndiffusion nearby. You might be able to get ask them to waive the error.

It is definitely possible to get a waiver for the

IO

rules; the Calibre rule deck has those rules in a block surrounded by some

*NOWAIVE

definition that looks like something that can be set with a checkbox in the DRC run setup.

How can we be sure that the IO.3a2 can be waive? @Juan Sebastian Moya

The device was created for sky130 and ported to GF. But I agree with Mitch that there is no reason to believe that there will be latchup issues with this device, and I would recommend going for the waiver.

How can we request to waive those drc errors in this case?

It's a request that needs to be made to the foundry at the time of submission, or else the foundry will send back a list of DRC errors and they can be waived at that time.

In LTC2, Japan block is also facing IO errors of IO.1a2, IO.3a1, IO.4. Is it possible to waive these errors?

@Akira Tsuchiya your question is buried in a thread that the people who make the decision may not see. Can you repost to the channel? My personal opinion is that for test chips, latchup rule drc errors are probably not going to result in an unusable chip. However, I’m not the one making the final decision.