I looked up the rules, both of which relate to having double guard rings around devices that connect directly to an I/O pad. (One rule is for N-diffusion surrounded by a P-substrate guard ring surrounded by an N-well guard ring, and the other rule is for P-diffusion surrounded by an N-well guard ring surrounded by a P-substrate guard ring).

@Tim Edwards what could be wrong with this?

Two p-substrate guard rings don't count as a double guard ring structure. The outer guard ring around your nFET devices needs to be an N-well guard ring.

So as far as i understand i have to put nwell guard ring over this whole circuit . Is that right

If you added an n-well guard ring around that structure, it should suffice, yes.

It will be helpful if you can give example circuit or i can change circuit to let you know if that you mean

Your transistors connected to the pad should look like this (I can't tell if the third device in your screenshot above is connected directly to the pad or not; if so, then it also needs double guard rings):

@Tim Edwards by putting like double guard ring IO.3a2 and IO.1a2 are gone but a new error like IO.1a2.nwell_guard-dev something like that come

It says that the nwell used as the guard ring cannot be used as the well for a pFET.

Yes exactly

@Atif Khan I’m thinking that you don’t want to put nwell guard ring over the whole circuit, just around the nmos. I think you want something like this.

@Mitch Bailey is this structure right, now mu question is yesterday i was trying to do it like that those two error were gone but IO.4 and IO.2 are coming which are about guard ring size