Hello people. I making the layout of a circuit and...
# magic
h
Hello people. I making the layout of a circuit and in that circuit this one n transistor. I have connected the drain of the transistor to 'down_b', gate to 'gnd', source and substrate to 'test'. However in the extracted spice file I see that only one terminal is connected to 'down_b' while all others are grounded. why is that ? also in spice files we have transsitor pin ordering as 'drain gate source substrate'. does the pin ordering changed in layout extracted spice file ?
t
Well you have other transistors in there. If the guard ring / bulk of those is connected to GND, then
test
is connected to ground too via the substrate ...
l
Regarding pin order, once Magic extracts the netlist it creates one subcircuit for each of your instantiated devices (more precisely, for each different device hash - the string at the end of the device's names). The pinout of these subcircuits is "random," and you will have to take a look at them to check the pin order of the MOSFET connections. These subcircuits should be located at the beginning or the end of the extracted netlist.
h
thanks @Lucas Daudt Franck
@tnt I isolated one nfet and then labeled it as follows. the source , drain and substrate are tied to 'down_b'. while the gate is connected to 'test'. the extracted netlist list should be like 'test down_b down_b down_b' but instead i see VSUB (left image is the netlist)
while doing the same in a pfet gives correct netlist
t
Because your pfet is alone in its nwell ... all your nfets share the same substrate.
h
how do i solve the issue. i have other nfets also and some of their substrate need to connect to the gnd. where as this one's substrate needs to connect to a pin
l
This image may help you understand what is happening:
👍 1
t
You need to create a deep-n-well, then inside that deep-n-well create an insolated pwell.
And there you can bias that pwell to anything you want ( well, you need to make sure you're not creating any fwd biased diodes ... )
Magic should have a pcell / helper to create a deep n-well.
h
thanks for letting me know. i am a beginner with layouts. i created the below layout by importing a spice netlist and then wiring them. the black ones are the nfets who's substrate is connected to 'GND'. While the white ones' substrate need to go to a pin. Can you explain how i'll create a deep-n well here?
l
As @tnt mentioned, Magic has a deep Nwell generator in the devices tab (make sure to get the latest Magic version, as this feature was recently patched by Tim). You should place the NFETs for which you want isolated bulk connections inside these deep N "rings".
h
when I click the deep n well option, nothing happens. I installed magic 2 months ago. was it updated within this period?
l
Yes, you should update it. Additionally, you should check the console window to see if there are any error messages. Perhaps the selected area doesn't meet the minimum size required for it to work.
h
thanks @Lucas Daudt Franck i checked the terminal, there was indeed minimum size warning. now I have incorporated dnwells in my design. the layout is working as expected
1