hi @Tim Edwards / @Mitch Bailey / @Luis Henrique Rodovalho I am making the layout of 8x clock multiplier PLL (input frequency 5mhz to 12mhz). I have made the layouts for pfd, frequency divider (fd) and vco. Only (charge pump+loop filter) part is left. I have shown the loop filter and its parameters in the first picture. The values of the capacitor and resistor are crucial. Through my previous discussions in this channel. I came to know that these values are very large, and I tried decreased the values of the capacitors. The values that I have shown are the minimum I could afford. Below that the output distorts. When I import the same in magic. I get the cells imported as shown in the 3rd picture. The capacitors get a maximum to (30um x 30um) while in the schematic they were about 1000x125. Can you advice on how i can make the layout ?

You can always use multipliers. If not, you can use capacitor arrays. 139 x (30 x 30) ≈ 1 x (1000 x 125). And 100 ohm is still too small.

sure, i calculated the area of the loop filter as 0.13798mm2. The die area that i have is 10mm2. Lets see how other blocks go

Use both MiM cap layers and you can halve the area.

@Tim Edwards both mim cap layers ? I assume you are talking about these two. how can i use both together?

You can place them directly on top of one another.

The "double burger cap" 🙂

I am getting this warning when I simulate my layout. The output is also not as expected. am I doing something wrong with the poly resistor ?

@Himanshu Singh it's just a joke, I called this stacked MIM cap as "double burger" The 3 bread layers are M3, M4, M5 the meat in between is the oxide.

ya , i got the analogy. I was seeking the technique to do that

Note that bread is not a very good conductor, and tomato makes a lousy dielectric.

@Himanshu Singh Your charge-pump looks interesting, I’ve never seen it hooked up like that. Maybe it’s the way it’s drawn but I’m having trouble understanding how it works. The t-gate looking pair of pmos/nmos in the middle of the CP is most confusing to me as they appear to be tied off (nmos gate grounded and pmos gate tied to supply) Is it working as an accumulation mode cap and you’re using the parasitic Cgd/Cgs to pump? How does it work? Love to learn, thanks for posting it.