Can someone explain what that is ? It's like changing from

diff

to

tap

in the middle of the gate ?!?

It looks like you change from nsd on top and bottom to psd in the middle. If this is in substrate the GDS input took fom and made tap out of it.

I think it's in the substrate yes. (It's from the OpenRAM SRAM bitcell)

Oh, bit cell. Which macro?

Can you send me a link to the repo?

@tnt Are those dummy gates tied to vss?

That was my thought.

I have no idea, hence why I'm asking. I didn't even know changing from diff to tap in the middle of a device was a thing. What's the benefit ? And why would you have dummy gates ?

Dummy gates are tied off so a channel never forms. You use them in analog design for matching. In this case it might be they are trying to get a tap contact in but don't have room for diff to tap to diff spacing. Is there a licon on the tap?

Yes, there is a licon there indeed.

There you go. If you want to verify, go check the TDR for diff overlap of licon, diff to tap space, and tap overlap of licon rules, and compare to this.

So the whole point was just to get a

tap

to connect substrate to

GND

and just be smaller ? That poly on top is also connected to

GND

.

Yep. The poly gate being connected to ground means it is always off, isolating the two regions. I'm not sure if this is a core only rule or not. You'll need to check the TDR.

@David Lindley Thanks.

FYI: In the SRAM bit cell, there are a lot of rules bent to compress the thing into a tiny size. That includes ends of poly tucked under diffusion, forming a partial transistor that acts as a MOScap, and diffusion transitioning to tap under a gate, as shown in the picture at top. And yes, magic doesn't support it because there are a whole slew of special DRC rules for just the SRAM core. Users should not be allowed to follow these rules anyway, because they only work with the SRAM macro, having been vetted by the design team that made the SRAM core cell. Since those rules can't be used for design, I opted to have magic ignore those rules, and just treat the whole SRAM macro as an abstract view when running DRC in magic.

@Tim Edwards Ack, yeah make sense to not bother implementing them if you can't use them. I was just wondering if I could use such tricks in my own cells design. I knew the the small transistor size were limited to the sram bitcell but I didn't know there was other stuff like that.

The SRAM cell layouts are scrutinized by a lot of folks in Design, Technology, and Fab before approval is given to CAD to implement the rules.

@tnt I’ve seen dummy gates tied to ground for nmos and power for pmos used to split diffusion. The minimum gate length is often shorter than minimum diffusion spacing.

@Mitch Bailey Yes indeed, diff2diff would be 0.27u which is way larger than 0.15u gate length.