Hi All - Can each group lead send me a short description of their blocks + Specify their testchip ASAP. Thanks!

BRACOLIN (LTC3) Brazil: • Current controlled band-pass filter Hz/kHz; • Clock Reference generator - 1Mhz; • Voltage reference - 1.3V; • LDO, Vin=1.3, Vout = 1.65V; • Inverter and transistors for characterization (if space/pins). Colombia (@Juan Sebastian Moya): • SAR-ADC 11-bit Is this enough ? Or you need more description in a separated file ?

this is great!

@mehdi Pakistan: 1). Low phase noise, Programmable differential clock generator. (PLL) • frequency Range (1MHz - 130 MHz) • 7 bit feed back divider (50% Duty cycle and full modulus range) • Step size of 1MHz • jitter 400 fs • Lock Time 40 us 2). Phase locked loop based tunable clock generator for ADC and DAC (PLL). • frequency Range (8 MHz - 220 MHz) • 50% Duty cycle • jitter 500 fs • Lock Time 27 us • Reference 2 MHz

Japan: 1. clock generator PLL: • reference clock: 8 MHz • clock frequency: 48 MHz 2. voltage reference: • 1.2 V output

Chile (LTC-TEAM2, same as Japan and Korea) • 2 LDOs, Vin = 5V, Vout = 3.3V • one of the LDOs is open loop for stability measurements

Korea (LTC-TEAM2, same as Japan and Chile) DAC : • # of bits : 10 • maximum sampling rate : 50MS/s • nominal current of 1LSB : 10uA