When I use Opelane2, KLayout DRC is skepped becasue openlane says "KLayout DRC is not supported for gf180mcuD PDK" as below. After generating, I opened the result of gds in final/klayout_gds, but it has a lot of DRC errors How can I consider this error?

@Junbeom Park What about

final/magic_gds

. Does that give the same drc errors in klayout?

@Mitch Bailey Oh! it is clean to import magic_gds file! Thank you!

I haven’t tried doing digital LVS on openlane output in klayout.

Using the result of Openlane, I can simulate with spice netlist from openlane in Xschem.

What result of openlane? extracted gds? verilog? Is there a spice netlist output of openlane?

Layout : gds from openlane + what I drawed manually Schematic : spice from openlane + what I drawed manually but spice from openlane has black box effect

What directory is the spice from openlane output?

In case of my design : "/home/junbeom/pico/designs/openlane/dac_matrix_decoder/runs/RUN_2024-04-20_15-34-59/final/spice/dac_matrix_decoder.spice" = [RUN directory]/final/spice/[design.spice]

Thanks!

Does it mean that without other circuits, the layout should compared alone with spice?

@Junbeom Park Sorry, I’m not sure what you’re asking. You’re doing a mixed signal, analog and digital, design, correct? The openlane output has already passed an abstract LVS - LVS at the cell level instead of the device level. Your combined layout also needs to pass LVS. These are your source netlists: A: Analog circuit spice from xschem C: Standard cell spice from pdk D: Digital circuit gate level verilog from openlane When openlane passes LVS, that is essentially saying that D: Digital circuit gate level verilog = D’: Digital extracted layout So for your top level source, you’re using A+C+D’ which is logically equivalent, but I personally feel more comfortable using pure source netlists, if possible. However, I don’t know how to read verilog netlists into klayout LVS, so your solution may be the best at this time.

@Mitch Bailey Thank you. I'm trying to lvs only with a generated block... but not matching

Using klayout right?

yes

I’ll see if I can put a verilog -> spice conversion script together tomorrow. Can you share your

verilog/gl/dac_matrix_decoder.v

file?

you mean the verilog file I used to generate this block? I'm not sure

verilog/gl/dac_matrix_decoder.v

<-- where is this directory. but attached file is used.

Not the rtl. Running openlane should have created a power gate level verilog netlist. I assumed it would be in the

verilog/gl

directory. If not, you might be able to find it with

find . -name dac_matrix_decoder.v

Look at the file and if its a structural netlist with power connections.

OMG. using above command, I can only find RTL file. Is something wrong???