how can I remove parasitic capacitance in post-layout simulation

What tool is generating the netlist being simulated?

we are actually using "ext2spice cthresh 0.1" command in magic's tkcon window to extract the parasitic capacitance from mag file.

Then you just answered your own question. Don't use that command and you won't get parasitic capacitance in the output.

"ext2spice cthresh 0.1" is used to extract any parasitic capacitances formed while drawing the layout, isn't?

You asked how to remove parasitic capacitances in post-layout simulation.

yes