Incorporating logic analyzer with analog_io is causing slew violations. A logic analyzer is used to take some numerical values. And then based on it, the analog_io is turned high. It is showing a slew violation for analo_io while hardening the user project wrapper.I tried PL_RESIZER_MAX_SLEW_MARGIN":25, "GLB_RESIZER_MAX_SLEW_MARGIN":15, "SYNTH_STRATEGY":"DELAY 0", It looks like it has no effect on slew vialations

@Md Omar Faruque There’s a detailed discussion of slew and other timing problems here. I’m not an expert, but I think slew violations are caused by signals being too weak to drive the associated load. For logic signals, increasing the driver size or adding buffers may solve the problem. There are parameters in the openlane config file that relate to resizing and buffering. For external input analog signal slew problems, • you may or may not want to add an analog buffer (they tend to be big). • You might consider placing the circuit closer to the io pad to reduce wire length. • Making the path wider will reduce resistance (but add capacitance - and I don’t know how to specify wide signals in openlane). • With external signals, the drive strength is probably set at a default level in one of the input files (sdc?). If your external signal is actually stronger than the default setting, maybe all you have to do is change the drive strength to reflect the actual value. Anyone with more knowledge, please correct me.

analog_io

should always be marked as a false path; you don't want the digital synthesis tools to be analyzing analog paths as if they are digital signals. I would advise not to let openlane touch any analog part of a circuit.

How to indicate this?

@GS In openlane, I believe you use the

RSZ_DONT_TOUCH

configuration variable.