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Hello people, I was making a testbench for a Phase...
# sky130
h
Hello people, I was making a testbench for a Phase frequency detector. For the testbench I made a symbol. I provided inputs and power/gnd rails to the symbol and simulated it. I get the following error. I think I would need some guidance on how to deal with VPWR and GND ports of the gates.
m
@Himanshu Singh Can you share your netlists?
h
s
@Himanshu Singh you are including the spice models and doing all the spice commands in the lower level schematics. Move the .include and .lib and commands to top level testbench. Go to the lower level schematic by clicking symbol and pressing 'e', click the code block, do 'Ctrl-x' to cut, go back to top (ctrl-e, save lower level) and paste (ctrl-v) in the top level testbench.
h
ok i'll do that. I had a doubt in vpwr and gnd pins of gates. in the lower-level schematic, there are no visible pins for these. so how will I extract them in a symbol
s
in logic gates vpwr and gnd are assigned via attributes. Click on a gate , press 'q' and you will se the power rails / well assignments:
h
yes, but there should be a vsource named VPWR right
s
VPWR is the name of the supply node. You are setting VPWR to 1.8V in the testbench and this is enough. No need to have an additional power source inside the pfd.
Just keep the 
gnd
and 
vpwr
pins in the pfd schematic and remove the 1.8V voltage source in between
h
ok
hi @Stefan Schippers / @Luis Henrique Rodovalho / @Mitch Bailey this is my layout for a phase frequency detector. I made this by importing the spice file for the pfd schematic. the spice file had 2 input and 2 output pins. these pins are reflected in the layout below. apart from this do i also need to import VPWR and GND pins ?
m
You’ll need to connect power and ground to the mos supplies. You’ll also need to add nwell and psub taps.
v
As suggested by @Mitch Bailey nwell and psub taps can be connected using this cell in your layout: 
/usr/local/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/mag/sky130_fd_sc_hd__tapvpwrvgnd_1.mag
h
Thanks @vks , @Mitch Bailey I had provided the power and the ground rails by a 'V3 VPWR GND 1.8v' in the testbench netlist file. The testbench was prepared by providing stimulus to the symbol of the schematic. And then replacing the schematic subckt with the layout subckt. Can you please provide a YouTube tutorial showing implementation of a 'gate' based design on magic ?
pfd_lay.spicepfd_lay_tb.spice
l
v
@Himanshu Singh Can you be specific about your issue to suggest something? Also what do you imply by 
replacing the schematic subckt with the layout subckt
?
l
See his layout

https://open-source-silicon.slack.com/files/U02NTJQUQ8K/F06TQMWKN1Z/image.png▾

All cells are joined together and the below row is flipped, so the power rails are merged.
h
yes @Luis Henrique Rodovalho you had suggested this before. but every gate has their own vdd and gnd labelled right ? so how does this make a difference? also I just wanted to test if the layout works. that is why I didnt do tight packing.
l
The problem of you layout is that you didn't put pins for power in the top cell
.subckt pfd_lay f_clk_in up f_vco down Xx1 x7/Y x9/B x7/A x2/Y x1/VGND VSUBS x1/VPB x1/VPWR x9/A sky130_fd_sc_hd__nand4_1 Xx3 f_clk_in x3/VGND VSUBS x6/VPB x3/VPWR x6/B sky130_fd_sc_hd__inv_1 Xx2 x5/Y x2/B x2/VGND VSUBS x2/VPB x2/VPWR x2/Y sky130_fd_sc_hd__nand2_1 Xx4 x9/A x4/B x7/Y x4/VGND VSUBS x6/VPB x4/VPWR x6/A sky130_fd_sc_hd__nand3_1 Xx5 x9/A x5/B x9/B x5/VGND VSUBS x5/VPB x5/VPWR x5/Y sky130_fd_sc_hd__nand3_1 Xx6 x6/A x6/B x6/VGND VSUBS x6/VPB x6/VPWR x7/A sky130_fd_sc_hd__nand2_1 Xx7 x7/A x7/B x7/VGND VSUBS x7/VPB x7/VPWR x7/Y sky130_fd_sc_hd__nand2_1 Xx9 x9/A x9/B x9/VGND VSUBS x9/VPB x9/VPWR x9/Y sky130_fd_sc_hd__nand2_1 Xx10 x7/A x10/VGND VSUBS x6/VPB x10/VPWR x12/A sky130_fd_sc_hd__inv_1 Xx11 x9/Y x2/Y x11/VGND VSUBS x9/VPB x11/VPWR x9/B sky130_fd_sc_hd__nand2_1 Xx12 x12/A x12/VGND VSUBS x6/VPB x12/VPWR x4/B sky130_fd_sc_hd__inv_1 Xsky130_fd_sc_hd__nand2_1_0 x7/Y x9/A sky130_fd_sc_hd__nand2_1_0/VGND VSUBS x7/VPB + sky130_fd_sc_hd__nand2_1_0/VPWR x7/B sky130_fd_sc_hd__nand2_1 Xx13 f_vco x13/VGND VSUBS x2/VPB x13/VPWR x2/B sky130_fd_sc_hd__inv_1 Xx15 x15/A x15/VGND VSUBS x2/VPB x15/VPWR x5/B sky130_fd_sc_hd__inv_1 Xx14 x2/Y x14/VGND VSUBS x2/VPB x14/VPWR x15/A sky130_fd_sc_hd__inv_1 Xx16 x6/A x16/VGND VSUBS x6/VPB x16/VPWR up sky130_fd_sc_hd__inv_1 Xx17 x5/Y x17/VGND VSUBS x5/VPB x17/VPWR down sky130_fd_sc_hd__inv_1 .ends
See your subckt. There is no power pin. And all your subcells have their own gnd. For example, x1/vgnd for xx1 instance and x2/vgnd for xx2 instance
So, what you must do is: Name all your nets, so you can read the generated netlist easier. Connect all your logic gate instances power nets together and connect it to extra power pins. Put a tap standard cell there, so you won't have vsub nets.
h
@Luis Henrique Rodovalho appreciate the help. earlier I was trying to connect all gates together. but in that case wiring was very difficult
l
No problem. You still need to connect all supplies. Later you can try to shrink it. Now it is time to have a functional circuit. Later you can improve it.
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