open-source-silicon.dev

I haven't compared both netlists bit by bit, but at first glance you can see that the models in `comp_14.spice` have some extra parameters, such as AD (drain area), PD (drain perimeter), AS (source area), and PS (source perimeter). These parameters add parasitic capacitances to the design which may be the cause of your results.

That would be my starting point. Maybe somebody else with more experience could give you a better insight.

<@U06JDGN07LM> As <@U06KKMED5C3> mentioned, the comp_14.spice netlist here is an LVS netlist, which you can simulate, but creating a simulation netlist with `Simulation` -&gt; `LVS netlist: top level is a .subckt` unchecked might give you a better result. This netlist will probably work best if you create a test bench that instantiates `comp_14` rather than netlisting `comp_14` directly.

The netlist extracted from gds has not been flattened and flattening may solve some of the issues. A quick way to flatten pcells (which may not be sufficient for parasitic resistance extraction), is to add this line before `gds read &lt;filename&gt;`
```gds flatglob {sky130_fd_pr__*[A-Z]*}```

Ok <@U017X0NM2E7> <@U06KKMED5C3>. Thank you so much for your help. :slightly_smiling_face: